arm-trusted-firmware/include/lib/cpus/aarch64
Boyan Karatotev 2590e819eb perf(mpmm): greatly simplify MPMM enablement
MPMM is a core-specific microarchitectural feature. It has been present
in every Arm core since the Cortex-A510 and has been implemented in
exactly the same way. Despite that, it is enabled more like an
architectural feature with a top level enable flag. This utilised the
identical implementation.

This duality has left MPMM in an awkward place, where its enablement
should be generic, like an architectural feature, but since it is not,
it should also be core-specific if it ever changes. One choice to do
this has been through the device tree.

This has worked just fine so far, however, recent implementations expose
a weakness in that this is rather slow - the device tree has to be read,
there's a long call stack of functions with many branches, and system
registers are read. In the hot path of PSCI CPU powerdown, this has a
significant and measurable impact. Besides it being a rather large
amount of code that is difficult to understand.

Since MPMM is a microarchitectural feature, its correct placement is in
the reset function. The essence of the current enablement is to write
CPUPPMCR_EL3.MPMM_EN if CPUPPMCR_EL3.MPMMPINCTL == 0. Replacing the C
enablement with an assembly macro in each CPU's reset function achieves
the same effect with just a single close branch and a grand total of 6
instructions (versus the old 2 branches and 32 instructions).

Having done this, the device tree entry becomes redundant. Should a core
that doesn't support MPMM arise, this can cleanly be handled in the
reset function. As such, the whole ENABLE_MPMM_FCONF and platform hooks
mechanisms become obsolete and are removed.

Change-Id: I1d0475b21a1625bb3519f513ba109284f973ffdf
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>
2025-02-25 08:50:45 +00:00
..
a64fx.h feat(cpus): add a64fx cpu to tf-a 2022-07-07 07:17:25 +09:00
aem_generic.h chore: update to use Arm word across TF-A 2023-08-08 15:12:30 +01:00
cortex_a35.h feat(cpufeat): add cortex-a35 l2 extended control register 2024-01-26 11:00:43 +08:00
cortex_a53.h chore: update to use Arm word across TF-A 2023-08-08 15:12:30 +01:00
cortex_a55.h chore: update to use Arm word across TF-A 2023-08-08 15:12:30 +01:00
cortex_a57.h chore: update to use Arm word across TF-A 2023-08-08 15:12:30 +01:00
cortex_a65.h Introducing support for Cortex-A65 2019-10-02 18:12:28 +02:00
cortex_a65ae.h Introducing support for Cortex-A65AE 2019-10-03 15:38:31 +02:00
cortex_a72.h chore: update to use Arm word across TF-A 2023-08-08 15:12:30 +01:00
cortex_a73.h chore: update to use Arm word across TF-A 2023-08-08 15:12:30 +01:00
cortex_a75.h fix(cpus): modify the fix for Cortex-A75 erratum 764081 2024-10-03 10:07:47 -05:00
cortex_a76.h refactor(cpus): convert the Cortex-A76 to use the errata framework 2023-08-03 14:10:28 -05:00
cortex_a76ae.h fix(security): workaround for CVE-2022-23960 for A76AE, A78AE, A78C 2022-03-21 08:57:09 -05:00
cortex_a77.h chore: update to use Arm word across TF-A 2023-08-08 15:12:30 +01:00
cortex_a78.h chore: update to use Arm word across TF-A 2023-08-08 15:12:30 +01:00
cortex_a78_ae.h chore: update to use Arm word across TF-A 2023-08-08 15:12:30 +01:00
cortex_a78c.h fix(cpus): workaround for Cortex-A78C erratum 2743232 2023-11-20 16:44:28 -06:00
cortex_a510.h refactor(cpus): convert the Cortex-A510 to use cpu helpers 2023-07-27 09:35:12 +01:00
cortex_a520.h feat(cpus): workaround for Cortex-A520(2938996) and Cortex-X4(2726228) 2024-08-17 09:37:55 +01:00
cortex_a710.h fix(cpus): workaround for Cortex-A710 erratum 3701772 2025-02-03 10:14:33 -06:00
cortex_a715.h fix(cpus): workaround for Cortex-A715 erratum 3699560 2025-02-03 10:14:33 -06:00
cortex_a720.h fix(cpus): workaround for Cortex-A720 erratum 3699561 2025-02-03 13:57:26 -06:00
cortex_a720_ae.h fix(cpus): workaround for Cortex-A720-AE erratum 3699562 2025-02-03 13:57:50 -06:00
cortex_a725.h fix(cpus): workaround for Cortex-A725 erratum 3699564 2025-02-03 13:57:50 -06:00
cortex_alto.h fix(cpus): avoid SME related loss of context on powerdown 2025-02-03 14:29:47 +00:00
cortex_arcadia.h feat(cpus): add support for arcadia cpu 2024-10-17 09:34:03 -05:00
cortex_gelas.h Merge changes I765a7fa0,Ic33f0b6d,I8d1a88c7,I381f96be,I698fa849, ... into integration 2025-02-11 16:52:18 +01:00
cortex_x1.h fix(security): workaround for CVE-2022-23960 for Cortex-X1 2022-05-11 15:24:37 +02:00
cortex_x2.h fix(cpus): workaround for Cortex-X2 erratum 3701772 2025-02-03 13:57:50 -06:00
cortex_x3.h fix(cpus): workaround for Cortex-X3 erratum 3701769 2025-02-03 13:57:50 -06:00
cortex_x4.h fix(cpus): workaround for Cortex-X4 erratum 3701758 2025-02-03 13:57:50 -06:00
cortex_x925.h fix(cpus): workaround for Cortex-X925 erratum 3701747 2025-02-03 13:57:50 -06:00
cpu_macros.S perf(mpmm): greatly simplify MPMM enablement 2025-02-25 08:50:45 +00:00
cpuamu.h chore: update to use Arm word across TF-A 2023-08-08 15:12:30 +01:00
denver.h chore: update to use Arm word across TF-A 2023-08-08 15:12:30 +01:00
dsu_def.h refactor(cpus): register DSU errata with the errata framework's wrappers 2025-02-20 17:28:17 +00:00
dsu_macros.S refactor(cpus): register DSU errata with the errata framework's wrappers 2025-02-20 17:28:17 +00:00
generic.h fix(tree): correct some typos 2023-05-09 15:57:12 +01:00
neoverse_e1.h chore: update to use Arm word across TF-A 2023-08-08 15:12:30 +01:00
neoverse_n1.h chore: update to use Arm word across TF-A 2023-08-08 15:12:30 +01:00
neoverse_n2.h fix(cpus): workaround for Neoverse-N2 erratum 3701773 2025-02-03 13:57:50 -06:00
neoverse_n3.h fix(cpus): workaround for Neoverse-N3 erratum 3699563 2025-02-03 13:57:50 -06:00
neoverse_v1.h fix(cpus): workaround for Neoverse V1 erratum 2348377 2023-11-20 16:29:40 -06:00
neoverse_v2.h fix(security): add CVE-2024-7881 mitigation to Neoverse-V2 2025-01-30 16:45:35 -06:00
neoverse_v3.h fix(cpus): workaround for Neoverse-V3 erratum 3701767 2025-02-03 13:57:51 -06:00
nevis.h feat(cpus): add support for Nevis CPU 2023-08-28 13:18:20 -05:00
qemu_max.h chore: update to use Arm word across TF-A 2023-08-08 15:12:30 +01:00
rainier.h lib/cpus: update MIDR value for rainier cpu 2020-10-09 10:43:13 +00:00
travis.h fix(cpus): avoid SME related loss of context on powerdown 2025-02-03 14:29:47 +00:00