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d732300b86
Cortex-A725 erratum 3699564 that applies to r0p0, r0p1 and is fixed in r0p2. The workaround is for EL3 software that performs context save/restore on a change of Security state to use a value of SCR_EL3.NS when accessing ICH_VMCR_EL2 that reflects the Security state that owns the data being saved or restored. SDEN documentation: https://developer.arm.com/documentation/SDEN-2832921/latest Change-Id: Ifad1f6c3f5b74060273f897eb5e4b79dd9f088f7 Signed-off-by: Govindraj Raja <govindraj.raja@arm.com>
28 lines
974 B
C
28 lines
974 B
C
/*
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* Copyright (c) 2023-2025, Arm Limited. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef CORTEX_A725_H
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#define CORTEX_A725_H
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#define CORTEX_A725_MIDR U(0x410FD870)
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/*******************************************************************************
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* CPU Extended Control register specific definitions
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******************************************************************************/
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#define CORTEX_A725_CPUECTLR_EL1 S3_0_C15_C1_4
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#define CORTEX_A725_CPUECTLR_EL1_EXTLLC_BIT U(0)
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/*******************************************************************************
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* CPU Power Control register specific definitions
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******************************************************************************/
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#define CORTEX_A725_CPUPWRCTLR_EL1 S3_0_C15_C2_7
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#define CORTEX_A725_CPUPWRCTLR_EL1_CORE_PWRDN_BIT U(1)
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#ifndef __ASSEMBLER__
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long check_erratum_cortex_a725_3699564(long cpu_rev);
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#endif /* __ASSEMBLER__ */
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#endif /* CORTEX_A725_H */
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