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feat(cpus): workaround for Cortex-A520(2938996) and Cortex-X4(2726228)
This patch implements errata functions for two errata, both of them
disable TRBE as a workaround. This patch doesn't have functions
that disable TRBE but only implemented helper functions that are
used to detect cores affected by Errata 2938996(Cortex-A520) & 2726228(Cortex-X4)
Cortex-X4 SDEN documentation:
https://developer.arm.com/documentation/SDEN2432808/latest
Cortex-A520 SDEN Documentation:
https://developer.arm.com/documentation/SDEN-2444153/latest
Signed-off-by: Arvind Ram Prakash <arvind.ramprakash@arm.com>
Change-Id: I8f886a1c21698f546a0996c719cc27dc0a23633a
This commit is contained in:
Arvind Ram Prakash
Manish Pandey
parent
7754b770cf
commit
4a97ff5111
7 changed files with 90 additions and 6 deletions
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@ -826,6 +826,10 @@ For Cortex-X4, the following errata build flags are defined :
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feature is enabled and can assist the Kernel in the process of
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mitigation of the erratum.
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- ``ERRATA_X4_2726228``: This applies erratum 2726228 workaround to Cortex-X4
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CPU. This needs to be enabled for revisions r0p0 and r0p1. It is fixed in
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r0p2.
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- ``ERRATA_X4_2740089``: This applies errata 2740089 workaround to Cortex-X4
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CPU. This needs to be enabled for revisions r0p0 and r0p1. It is fixed
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in r0p2.
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@ -899,6 +903,10 @@ For Cortex-A520, the following errata build flags are defined :
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Cortex-A520 CPU. This needs to be enabled for revisions r0p0 and r0p1.
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It is still open.
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- ``ERRATA_A520_2938996``: This applies errata 2938996 workaround to
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Cortex-A520 CPU. This needs to be enabled for revisions r0p0 and r0p1.
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It is fixed in r0p2.
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For Cortex-A715, the following errata build flags are defined :
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- ``ERRATA_A715_2331818``: This applies errata 2331818 workaround to
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@ -28,4 +28,15 @@
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#define CORTEX_A520_CPUPWRCTLR_EL1 S3_0_C15_C2_7
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#define CORTEX_A520_CPUPWRCTLR_EL1_CORE_PWRDN_BIT U(1)
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#ifndef __ASSEMBLER__
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#if ERRATA_A520_2938996
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long check_erratum_cortex_a520_2938996(long cpu_rev);
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#else
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static inline long check_erratum_cortex_a520_2938996(long cpu_rev)
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{
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return 0;
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}
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#endif /* ERRATA_A520_2938996 */
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#endif /* __ASSEMBLER__ */
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#endif /* CORTEX_A520_H */
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@ -34,4 +34,15 @@
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#define CORTEX_X4_CPUACTLR5_EL1 S3_0_C15_C8_0
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#define CORTEX_X4_CPUACTLR5_EL1_BIT_14 (ULL(1) << 14)
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#ifndef __ASSEMBLER__
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#if ERRATA_X4_2726228
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long check_erratum_cortex_x4_2726228(long cpu_rev);
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#else
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static inline long check_erratum_cortex_x4_2726228(long cpu_rev)
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{
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return 0;
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}
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#endif /* ERRATA_X4_2726228 */
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#endif /* __ASSEMBLER__ */
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#endif /* CORTEX_X4_H */
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@ -25,12 +25,21 @@
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#define ERRATUM_MITIGATED ERRATUM_CHOSEN + ERRATUM_CHOSEN_SIZE
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#define ERRATUM_ENTRY_SIZE ERRATUM_MITIGATED + ERRATUM_MITIGATED_SIZE
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/* Errata status */
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#define ERRATA_NOT_APPLIES 0
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#define ERRATA_APPLIES 1
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#define ERRATA_MISSING 2
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#ifndef __ASSEMBLER__
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#include <lib/cassert.h>
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void print_errata_status(void);
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void errata_print_msg(unsigned int status, const char *cpu, const char *id);
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#if ERRATA_A520_2938996 || ERRATA_X4_2726228
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unsigned int check_if_affected_core(void);
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#endif
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/*
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* NOTE that this structure will be different on AArch32 and AArch64. The
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* uintptr_t will reflect the change and the alignment will be correct in both.
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@ -74,11 +83,6 @@ CASSERT(sizeof(struct erratum_entry) == ERRATUM_ENTRY_SIZE,
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#endif /* __ASSEMBLER__ */
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/* Errata status */
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#define ERRATA_NOT_APPLIES 0
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#define ERRATA_APPLIES 1
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#define ERRATA_MISSING 2
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/* Macro to get CPU revision code for checking errata version compatibility. */
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#define CPU_REV(r, p) ((r << 4) | p)
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@ -1,5 +1,5 @@
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/*
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* Copyright (c) 2021-2023, Arm Limited. All rights reserved.
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* Copyright (c) 2021-2024, Arm Limited. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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@ -11,6 +11,9 @@
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#include <cpu_macros.S>
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#include <plat_macros.S>
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/* .global erratum_cortex_a520_2938996_wa */
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.global check_erratum_cortex_a520_2938996
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/* Hardware handled coherency */
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#if HW_ASSISTED_COHERENCY == 0
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#error "Cortex A520 must be compiled with HW_ASSISTED_COHERENCY enabled"
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@ -32,6 +35,25 @@ workaround_reset_start cortex_a520, ERRATUM(2858100), ERRATA_A520_2858100
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workaround_reset_end cortex_a520, ERRATUM(2858100)
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check_erratum_ls cortex_a520, ERRATUM(2858100), CPU_REV(0, 1)
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workaround_runtime_start cortex_a520, ERRATUM(2938996), ERRATA_A520_2938996, CORTEX_A520_MIDR
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workaround_runtime_end cortex_a520, ERRATUM(2938996)
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check_erratum_custom_start cortex_a520, ERRATUM(2938996)
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/* This erratum needs to be enabled for r0p0 and r0p1.
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* Check if revision is less than or equal to r0p1.
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*/
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#if ERRATA_A520_2938996
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mov x1, #1
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b cpu_rev_var_ls
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#else
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mov x0, #ERRATA_MISSING
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#endif
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ret
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check_erratum_custom_end cortex_a520, ERRATUM(2938996)
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/* ----------------------------------------------------
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* HW will do the cache maintenance while powering down
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* ----------------------------------------------------
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@ -22,10 +22,30 @@
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#error "Cortex X4 supports only AArch64. Compile with CTX_INCLUDE_AARCH32_REGS=0"
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#endif
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.global check_erratum_cortex_x4_2726228
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#if WORKAROUND_CVE_2022_23960
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wa_cve_2022_23960_bhb_vector_table CORTEX_X4_BHB_LOOP_COUNT, cortex_x4
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#endif /* WORKAROUND_CVE_2022_23960 */
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workaround_runtime_start cortex_x4, ERRATUM(2726228), ERRATA_X4_2726228, CORTEX_X4_MIDR
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workaround_runtime_end cortex_x4, ERRATUM(2726228)
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check_erratum_custom_start cortex_x4, ERRATUM(2726228)
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/* This erratum needs to be enabled for r0p0 and r0p1.
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* Check if revision is less than or equal to r0p1.
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*/
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#if ERRATA_X4_2726228
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mov x1, #1
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b cpu_rev_var_ls
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#else
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mov x0, #ERRATA_MISSING
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#endif
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ret
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check_erratum_custom_end cortex_x4, ERRATUM(2726228)
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workaround_runtime_start cortex_x4, ERRATUM(2740089), ERRATA_X4_2740089
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/* dsb before isb of power down sequence */
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dsb sy
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@ -823,6 +823,10 @@ CPU_FLAG_LIST += ERRATA_X3_2779509
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# cpu and is fixed in r0p1.
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CPU_FLAG_LIST += ERRATA_X4_2701112
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# Flag to apply erratum 2726228 workaround during warmboot. This erratum
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# applies to all revisions <= r0p1 of the Cortex-X4 cpu, it is fixed in r0p2.
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CPU_FLAG_LIST += ERRATA_X4_2726228
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# Flag to apply erratum 2740089 workaround during powerdown. This erratum
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# applies to all revisions <= r0p1 of the Cortex-X4 cpu, it is fixed in r0p2.
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CPU_FLAG_LIST += ERRATA_X4_2740089
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@ -896,6 +900,10 @@ CPU_FLAG_LIST += ERRATA_A520_2630792
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# applies to revision r0p0 and r0p1 of the Cortex-A520 cpu and is still open.
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CPU_FLAG_LIST += ERRATA_A520_2858100
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# Flag to apply erratum 2938996 workaround during reset. This erratum
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# applies to revision r0p0 and r0p1 of the Cortex-A520 cpu and is fixed in r0p2.
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CPU_FLAG_LIST += ERRATA_A520_2938996
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# Flag to apply erratum 2331132 workaround during reset. This erratum applies
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# to revisions r0p0, r0p1 and r0p2. It is still open.
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CPU_FLAG_LIST += ERRATA_V2_2331132
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