fix(cpus): workaround for Cortex-A720-AE erratum 3699562

Cortex-A720-AE erratum 3699562 that applies to r0p0 and is still
Open.

The workaround is for EL3 software that performs context save/restore
on a change of Security state to use a value of SCR_EL3.NS when
accessing ICH_VMCR_EL2 that reflects the Security state that owns the
data being saved or restored.

SDEN documentation:
https://developer.arm.com/documentation/SDEN-3090091/latest/

Change-Id: Ib830470747822cac916750c01684a65cb5efc15b
Signed-off-by: Govindraj Raja <govindraj.raja@arm.com>

docs/design/cpu-specific-build-macros.rst

@@ -986,6 +986,12 @@ For Cortex-A720, the following errata build flags are defined :
    Cortex-A720 CPU. This needs to be enabled for revisions r0p0, r0p1
    and r0p2. It is still open.
 
+For Cortex-A720_AE, the following errata build flags are defined :
+
+-  ``ERRATA_A720_AE_3699562``: This applies errata 3699562 workaround
+   to Cortex-A715_AE CPU. This needs to be enabled for revisions r0p0.
+   It is still open.
+
 DSU Errata Workarounds
 ----------------------
 

include/lib/cpus/aarch64/cortex_a720_ae.h

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2024, Arm Limited. All rights reserved.
+ * Copyright (c) 2024-2025, Arm Limited. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -20,4 +20,8 @@
 #define CORTEX_A720_AE_CPUPWRCTLR_EL1			S3_0_C15_C2_7
 #define CORTEX_A720_AE_CPUPWRCTLR_EL1_CORE_PWRDN_BIT	U(1)
 
+#ifndef __ASSEMBLER__
+long check_erratum_cortex_a720_ae_3699562(long cpu_rev);
+#endif /* __ASSEMBLER__ */
+
 #endif /* CORTEX_A720_AE_H */

lib/cpus/aarch64/cortex_a720_ae.S

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2024, Arm Limited. All rights reserved.
+ * Copyright (c) 2024-2025, Arm Limited. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -21,6 +21,12 @@
 #error "Cortex-A720AE supports only AArch64. Compile with CTX_INCLUDE_AARCH32_REGS=0"
 #endif
 
+.global check_erratum_cortex_a720_ae_3699562
+
+add_erratum_entry cortex_a720_ae, ERRATUM(3699562), ERRATA_A720_AE_3699562, NO_APPLY_AT_RESET
+
+check_erratum_ls cortex_a720_ae, ERRATUM(3699562), CPU_REV(0, 0)
+
 cpu_reset_func_start cortex_a720_ae
 	/* Disable speculative loads */
 	msr	SSBS, xzr

lib/cpus/cpu-ops.mk

@@ -1015,6 +1015,11 @@ CPU_FLAG_LIST += ERRATA_A720_2940794
 # the Cortex-A720 cpu and is still open.
 CPU_FLAG_LIST += ERRATA_A720_3699561
 
+# Flag to apply erratum 3699562 workaround during context save/restore of
+# ICH_VMCR_EL2 reg. This erratum applies to revision r0p0 the Cortex-A720-AE
+# cpu and is still open.
+CPU_FLAG_LIST += ERRATA_A720_AE_3699562
+
 # Flag to apply DSU erratum 798953. This erratum applies to DSUs revision r0p0.
 # Applying the workaround results in higher DSU power consumption on idle.
 CPU_FLAG_LIST += ERRATA_DSU_798953

lib/cpus/errata_common.c

@@ -13,6 +13,7 @@
 #include <cortex_a710.h>
 #include <cortex_a715.h>
 #include <cortex_a720.h>
+#include <cortex_a720_ae.h>
 #include <cortex_x4.h>
 #include <lib/cpus/cpu_ops.h>
 #include <lib/cpus/errata.h>
@@ -68,6 +69,13 @@ bool errata_ich_vmcr_el2_applies(void)
 		break;
 #endif /* ERRATA_A720_3699561 */
 
+#if ERRATA_A720_AE_3699562
+	case EXTRACT_PARTNUM(CORTEX_A720_AE_MIDR):
+		if (check_erratum_cortex_a720_ae_3699562(cpu_get_rev_var()) == ERRATA_APPLIES)
+			return true;
+		break;
+#endif /* ERRATA_A720_AE_3699562 */
+
 	default:
 		break;
 	}