mirror of
https://github.com/ARM-software/arm-trusted-firmware.git
synced 2025-04-16 17:44:19 +00:00
af5ae9a73f
Cortex-A720-AE erratum 3699562 that applies to r0p0 and is still Open. The workaround is for EL3 software that performs context save/restore on a change of Security state to use a value of SCR_EL3.NS when accessing ICH_VMCR_EL2 that reflects the Security state that owns the data being saved or restored. SDEN documentation: https://developer.arm.com/documentation/SDEN-3090091/latest/ Change-Id: Ib830470747822cac916750c01684a65cb5efc15b Signed-off-by: Govindraj Raja <govindraj.raja@arm.com>
84 lines
2.1 KiB
C
84 lines
2.1 KiB
C
/*
|
|
* Copyright (c) 2024-2025, Arm Limited and Contributors. All rights reserved.
|
|
*
|
|
* SPDX-License-Identifier: BSD-3-Clause
|
|
*/
|
|
|
|
/* Runtime C routines for errata workarounds and common routines */
|
|
|
|
#include <arch.h>
|
|
#include <arch_helpers.h>
|
|
#include <cortex_a75.h>
|
|
#include <cortex_a520.h>
|
|
#include <cortex_a710.h>
|
|
#include <cortex_a715.h>
|
|
#include <cortex_a720.h>
|
|
#include <cortex_a720_ae.h>
|
|
#include <cortex_x4.h>
|
|
#include <lib/cpus/cpu_ops.h>
|
|
#include <lib/cpus/errata.h>
|
|
|
|
#if ERRATA_A520_2938996 || ERRATA_X4_2726228
|
|
unsigned int check_if_affected_core(void)
|
|
{
|
|
uint32_t midr_val = read_midr();
|
|
long rev_var = cpu_get_rev_var();
|
|
|
|
if (EXTRACT_PARTNUM(midr_val) == EXTRACT_PARTNUM(CORTEX_A520_MIDR)) {
|
|
return check_erratum_cortex_a520_2938996(rev_var);
|
|
} else if (EXTRACT_PARTNUM(midr_val) == EXTRACT_PARTNUM(CORTEX_X4_MIDR)) {
|
|
return check_erratum_cortex_x4_2726228(rev_var);
|
|
}
|
|
|
|
return ERRATA_NOT_APPLIES;
|
|
}
|
|
#endif
|
|
|
|
#if ERRATA_A75_764081
|
|
bool errata_a75_764081_applies(void)
|
|
{
|
|
long rev_var = cpu_get_rev_var();
|
|
if (check_erratum_cortex_a75_764081(rev_var) == ERRATA_APPLIES) {
|
|
return true;
|
|
}
|
|
return false;
|
|
}
|
|
#endif /* ERRATA_A75_764081 */
|
|
|
|
bool errata_ich_vmcr_el2_applies(void)
|
|
{
|
|
switch (EXTRACT_PARTNUM(read_midr())) {
|
|
#if ERRATA_A710_3701772
|
|
case EXTRACT_PARTNUM(CORTEX_A710_MIDR):
|
|
if (check_erratum_cortex_a710_3701772(cpu_get_rev_var()) == ERRATA_APPLIES)
|
|
return true;
|
|
break;
|
|
#endif /* ERRATA_A710_3701772 */
|
|
|
|
#if ERRATA_A715_3699560
|
|
case EXTRACT_PARTNUM(CORTEX_A715_MIDR):
|
|
if (check_erratum_cortex_a715_3699560(cpu_get_rev_var()) == ERRATA_APPLIES)
|
|
return true;
|
|
break;
|
|
#endif /* ERRATA_A715_3699560 */
|
|
|
|
#if ERRATA_A720_3699561
|
|
case EXTRACT_PARTNUM(CORTEX_A720_MIDR):
|
|
if (check_erratum_cortex_a720_3699561(cpu_get_rev_var()) == ERRATA_APPLIES)
|
|
return true;;
|
|
break;
|
|
#endif /* ERRATA_A720_3699561 */
|
|
|
|
#if ERRATA_A720_AE_3699562
|
|
case EXTRACT_PARTNUM(CORTEX_A720_AE_MIDR):
|
|
if (check_erratum_cortex_a720_ae_3699562(cpu_get_rev_var()) == ERRATA_APPLIES)
|
|
return true;
|
|
break;
|
|
#endif /* ERRATA_A720_AE_3699562 */
|
|
|
|
default:
|
|
break;
|
|
}
|
|
|
|
return false;
|
|
}
|