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fix(cpus): modify the fix for Cortex-A75 erratum 764081

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Apply the mitigation only for the revision and variant
mentioned in the SDEN.

SDEN Documentation:
https://developer.arm.com/documentation/SDEN859515/latest

Change-Id: Ifda1f4cb32bdec9a9af29397ddc03bf22a7a87fc
Signed-off-by: Sona Mathew <sonarebecca.mathew@arm.com>
This commit is contained in:
Sona Mathew 2024-07-10 18:04:40 -05:00
parent cc3d73cc67
commit 7f152ea685
6 changed files with 39 additions and 8 deletions
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3
bl1/bl1.mk
View file

@ -19,7 +19,8 @@ BL1_SOURCES += bl1/${ARCH}/bl1_arch_setup.c \
ifeq (${ARCH},aarch64)
BL1_SOURCES += lib/cpus/aarch64/dsu_helpers.S \
lib/el3_runtime/aarch64/context.S
lib/el3_runtime/aarch64/context.S \
lib/cpus/errata_common.c
endif
ifeq (${TRUSTED_BOARD_BOOT},1)

7
include/lib/cpus/aarch64/cortex_a75.h
View file

@ -1,5 +1,5 @@
/*
* Copyright (c) 2017-2019, Arm Limited and Contributors. All rights reserved.
* Copyright (c) 2017-2024, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@ -50,6 +50,11 @@ unsigned int cortex_a75_amu_read_cpuamcntenset_el0(void);
unsigned int cortex_a75_amu_read_cpuamcntenclr_el0(void);
void cortex_a75_amu_write_cpuamcntenset_el0(unsigned int mask);
void cortex_a75_amu_write_cpuamcntenclr_el0(unsigned int mask);
#if ERRATA_A75_764081
long check_erratum_cortex_a75_764081(long cpu_rev);
#endif /* ERRATA_A75_764081 */
#endif /* __ASSEMBLER__ */
#endif /* CORTEX_A75_H */

9
include/lib/cpus/errata.h
View file

@ -35,6 +35,15 @@
void print_errata_status(void);
#if ERRATA_A75_764081
bool errata_a75_764081_applies(void);
#else
static inline bool errata_a75_764081_applies(void)
{
return false;
}
#endif
#if ERRATA_A520_2938996 || ERRATA_X4_2726228
unsigned int check_if_affected_core(void);
#endif

2
lib/cpus/aarch64/cortex_a75.S
View file

@ -10,6 +10,8 @@
#include <cpuamu.h>
#include <cpu_macros.S>
.global check_erratum_cortex_a75_764081
/* Hardware handled coherency */
#if HW_ASSISTED_COHERENCY == 0
#error "Cortex-A75 must be compiled with HW_ASSISTED_COHERENCY enabled"

12
lib/cpus/errata_common.c
View file

@ -10,6 +10,7 @@
#include <arch_helpers.h>
#include <cortex_a520.h>
#include <cortex_x4.h>
#include <cortex_a75.h>
#include <lib/cpus/cpu_ops.h>
#include <lib/cpus/errata.h>
@ -28,3 +29,14 @@ unsigned int check_if_affected_core(void)
return ERRATA_NOT_APPLIES;
}
#endif
#if ERRATA_A75_764081
bool errata_a75_764081_applies(void)
{
long rev_var = cpu_get_rev_var();
if (check_erratum_cortex_a75_764081(rev_var) == ERRATA_APPLIES) {
return true;
}
return false;
}
#endif /* ERRATA_A75_764081 */

14
lib/el3_runtime/aarch64/context_mgmt.c
View file

@ -89,13 +89,13 @@ static void setup_el1_context(cpu_context_t *ctx, const struct entry_point_info
| SCTLR_NTWI_BIT | SCTLR_NTWE_BIT;
}
#if ERRATA_A75_764081
/*
* If workaround of errata 764081 for Cortex-A75 is used then set
* SCTLR_EL1.IESB to enable Implicit Error Synchronization Barrier.
*/
sctlr_elx |= SCTLR_IESB_BIT;
#endif
if (errata_a75_764081_applies()) {
sctlr_elx |= SCTLR_IESB_BIT;
}
/* Store the initialised SCTLR_EL1 value in the cpu_context */
write_ctx_sctlr_el1_reg_errata(ctx, sctlr_elx);
@ -1070,14 +1070,16 @@ void cm_prepare_el3_exit(uint32_t security_state)
if ((scr_el3 & SCR_HCE_BIT) != 0U) {
/* Initialize SCTLR_EL2 register with reset value. */
sctlr_el2 = SCTLR_EL2_RES1;
#if ERRATA_A75_764081
/*
* If workaround of errata 764081 for Cortex-A75
* is used then set SCTLR_EL2.IESB to enable
* Implicit Error Synchronization Barrier.
*/
sctlr_el2 |= SCTLR_IESB_BIT;
#endif
if (errata_a75_764081_applies()) {
sctlr_el2 |= SCTLR_IESB_BIT;
}
write_sctlr_el2(sctlr_el2);
} else {
/*