Djam/arm-trusted-firmware
1
0
Fork 0
mirror of https://github.com/ARM-software/arm-trusted-firmware.git synced 2025-04-25 22:35:42 +00:00
Code Issues Projects Releases Packages Wiki Activity Actions

feat(cpus): add support for Nevis CPU

Browse source 
Adding basic CPU library code to support Nevis CPU

Change-Id: I399cc9b7b2d907b02b76ea2a3e5abb54e28fbf6c
Signed-off-by: Juan Pablo Conde <juanpablo.conde@arm.com>
This commit is contained in:
Juan Pablo Conde 2023-07-06 15:38:59 -05:00
parent 5f01b0b116
commit 549795895c
3 changed files with 82 additions and 1 deletions
include/lib/cpus/aarch64
nevis.h
lib/cpus/aarch64
nevis.S
plat/arm/board/fvp
platform.mk

23
include/lib/cpus/aarch64/nevis.h Normal file
View file

@ -0,0 +1,23 @@
/*
* Copyright (c) 2023, Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef NEVIS_H
#define NEVIS_H
#define NEVIS_MIDR U(0x410FD8A0)
/*******************************************************************************
* CPU Extended Control register specific definitions
******************************************************************************/
#define NEVIS_CPUECTLR_EL1 S3_0_C15_C1_4
/*******************************************************************************
* CPU Power Control register specific definitions
******************************************************************************/
#define NEVIS_IMP_CPUPWRCTLR_EL1 S3_0_C15_C2_7
#define NEVIS_IMP_CPUPWRCTLR_EL1_CORE_PWRDN_EN_BIT U(1)
#endif /* NEVIS_H */

57
lib/cpus/aarch64/nevis.S Normal file
View file

@ -0,0 +1,57 @@
/*
* Copyright (c) 2023, Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#include <arch.h>
#include <asm_macros.S>
#include <common/bl_common.h>
#include <nevis.h>
#include <cpu_macros.S>
#include <plat_macros.S>
/* Hardware handled coherency */
#if HW_ASSISTED_COHERENCY == 0
#error "Nevis must be compiled with HW_ASSISTED_COHERENCY enabled"
#endif
/* 64-bit only core */
#if CTX_INCLUDE_AARCH32_REGS == 1
#error "Nevis supports only AArch64. Compile with CTX_INCLUDE_AARCH32_REGS=0"
#endif
cpu_reset_func_start nevis
/* ----------------------------------------------------
* Disable speculative loads
* ----------------------------------------------------
*/
msr SSBS, xzr
cpu_reset_func_end nevis
func nevis_core_pwr_dwn
/* ---------------------------------------------------
* Enable CPU power down bit in power control register
* ---------------------------------------------------
*/
sysreg_bit_set NEVIS_IMP_CPUPWRCTLR_EL1, \
NEVIS_IMP_CPUPWRCTLR_EL1_CORE_PWRDN_EN_BIT
isb
ret
endfunc nevis_core_pwr_dwn
errata_report_shim nevis
.section .rodata.nevis_regs, "aS"
nevis_regs: /* The ASCII list of register names to be reported */
.asciz "cpuectlr_el1", ""
func nevis_cpu_reg_dump
adr x6, nevis_regs
mrs x8, NEVIS_CPUECTLR_EL1
ret
endfunc nevis_cpu_reg_dump
declare_cpu_ops nevis, NEVIS_MIDR, \
nevis_reset_func, \
nevis_core_pwr_dwn

3
plat/arm/board/fvp/platform.mk
View file

@ -214,7 +214,8 @@ else
lib/cpus/aarch64/neoverse_v1.S \
lib/cpus/aarch64/neoverse_e1.S \
lib/cpus/aarch64/cortex_x2.S \
lib/cpus/aarch64/cortex_gelas.S
lib/cpus/aarch64/cortex_gelas.S \
lib/cpus/aarch64/nevis.S
endif
# AArch64/AArch32 cores
FVP_CPU_LIBS += lib/cpus/aarch64/cortex_a55.S \