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fix(cpus): workaround for Cortex-A78C erratum 2743232

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Cortex-A78C erratum 2743232 is a Cat B erratum that applies
to revisions r0p1 and r0p2 and is still open.
The workaround is to set CPUACTLR5_EL1[56:55] to 2'b01.

SDEN Documentation:
https://developer.arm.com/documentation/SDEN-2004089/latest

Change-Id: Ic62579c2dd69b7a8cbbeaa936f45b2cc9436439a
Signed-off-by: Sona Mathew <sonarebecca.mathew@arm.com>
This commit is contained in:
Sona Mathew 2023-11-14 14:00:48 -06:00
parent 71ed917331
commit 81d4094d63
5 changed files with 25 additions and 3 deletions
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4
docs/design/cpu-specific-build-macros.rst
View file

@ -389,6 +389,10 @@ For Cortex-A78C, the following errata build flags are defined :
an ARM interconnect IP. This needs to be enabled for revisions r0p1 and r0p2
and is still open.
- ``ERRATA_A78C_2743232`` : This applies erratum 2743232 workaround to
Cortex-A78C CPU. This needs to be enabled for revisions r0p1 and r0p2.
This erratum is still open.
- ``ERRATA_A78C_2772121`` : This applies errata 2772121 workaround to
Cortex-A78C CPU. This needs to be enabled for revisions r0p0, r0p1 and r0p2.
This erratum is still open.

5
include/lib/cpus/aarch64/cortex_a78c.h
View file

@ -47,4 +47,9 @@
#define CORTEX_A78C_IMP_CPUPOR_EL3 S3_6_C15_C8_2
#define CORTEX_A78C_IMP_CPUPMR_EL3 S3_6_C15_C8_3
/*******************************************************************************
* CPU Auxiliary Control register 5 specific definitions.
******************************************************************************/
#define CORTEX_A78C_ACTLR5_EL1 S3_0_C15_C9_0
#endif /* CORTEX_A78C_H */

8
lib/cpus/aarch64/cortex_a78c.S
View file

@ -72,6 +72,14 @@ workaround_reset_end cortex_a78c, ERRATUM(2395411)
check_erratum_range cortex_a78c, ERRATUM(2395411), CPU_REV(0, 1), CPU_REV(0, 2)
workaround_reset_start cortex_a78c, ERRATUM(2743232), ERRATA_A78C_2743232
/* Set CPUACTLR5_EL1[56:55] to 2'b01 */
sysreg_bit_set CORTEX_A78C_ACTLR5_EL1, BIT(55)
sysreg_bit_clear CORTEX_A78C_ACTLR5_EL1, BIT(56)
workaround_reset_end cortex_a78c, ERRATUM(2743232)
check_erratum_range cortex_a78c, ERRATUM(2743232), CPU_REV(0, 1), CPU_REV(0, 2)
workaround_runtime_start cortex_a78c, ERRATUM(2772121), ERRATA_A78C_2772121
/* dsb before isb of power down sequence */
dsb sy

4
lib/cpus/cpu-ops.mk
View file

@ -393,6 +393,10 @@ CPU_FLAG_LIST += ERRATA_A78C_2395411
# It is still open.
CPU_FLAG_LIST += ERRATA_A78C_2712575
# Flag to apply erratum 2743232 workaround during reset. This erratum applies
# to revisions r0p1 and r0p2 of the A78C cpu. It is still open.
CPU_FLAG_LIST += ERRATA_A78C_2743232
# Flag to apply erratum 2772121 workaround during powerdown. This erratum
# applies to revisions r0p0, r0p1 and r0p2 of the A78C cpu. It is still open.
CPU_FLAG_LIST += ERRATA_A78C_2772121

7
services/std_svc/errata_abi/errata_abi_main.c
View file

@ -239,9 +239,10 @@ struct em_cpu_list cpu_list[] = {
[5] = {2395411, 0x01, 0x02, ERRATA_A78C_2395411},
[6] = {2712575, 0x01, 0x02, ERRATA_A78C_2712575, \
ERRATA_NON_ARM_INTERCONNECT},
[7] = {2772121, 0x00, 0x02, ERRATA_A78C_2772121},
[8] = {2779484, 0x01, 0x02, ERRATA_A78C_2779484},
[9 ... ERRATA_LIST_END] = UNDEF_ERRATA,
[7] = {2743232, 0x01, 0x02, ERRATA_A78C_2743232},
[8] = {2772121, 0x00, 0x02, ERRATA_A78C_2772121},
[9] = {2779484, 0x01, 0x02, ERRATA_A78C_2779484},
[10 ... ERRATA_LIST_END] = UNDEF_ERRATA,
}
},
#endif /* CORTEX_A78C_H_INC */