fix(cpus): workaround for Neoverse-N3 erratum 3699563

Neoverse-N3 erratum 3699563 that applies to r0p0 is still Open.

The workaround is for EL3 software that performs context save/restore
on a change of Security state to use a value of SCR_EL3.NS when
accessing ICH_VMCR_EL2 that reflects the Security state that owns the
data being saved or restored.

SDEN documentation:
https://developer.arm.com/documentation/SDEN-3050973/latest/

Change-Id: I77aaf8ae0afff3adde9a85f4a1a13ac9d1daf0af
Signed-off-by: Govindraj Raja <govindraj.raja@arm.com>

docs/design/cpu-specific-build-macros.rst

@@ -732,6 +732,11 @@ For Neoverse N2, the following errata build flags are defined :
    CPU. This needs to be enabled for revisions r0p0, r0p1, r0p2, r0p3 and is
    still open.
 
+For Neoverse N3, the following errata build flags are defined :
+
+-  ``ERRATA_N3_3699563``: This applies errata 3699563 workaround to Neoverse-N3
+   CPU. This needs to be enabled for revisions r0p0 and is still open.
+
 For Cortex-X2, the following errata build flags are defined :
 
 -  ``ERRATA_X2_2002765``: This applies errata 2002765 workaround to Cortex-X2

include/lib/cpus/aarch64/neoverse_n3.h

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2023-2024, Arm Limited. All rights reserved.
+ * Copyright (c) 2023-2025, Arm Limited. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -21,4 +21,8 @@
 #define NEOVERSE_N3_CPUPWRCTLR_EL1			S3_0_C15_C2_7
 #define NEOVERSE_N3_CPUPWRCTLR_EL1_CORE_PWRDN_BIT	U(1)
 
+#ifndef __ASSEMBLER__
+long check_erratum_neoverse_n3_3699563(long cpu_rev);
+#endif /* __ASSEMBLER__ */
+
 #endif /* NEOVERSE_N3_H */

lib/cpus/aarch64/neoverse_n3.S

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2023-2024, Arm Limited. All rights reserved.
+ * Copyright (c) 2023-2025, Arm Limited. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -21,6 +21,12 @@
 #error "Neoverse-N3 supports only AArch64. Compile with CTX_INCLUDE_AARCH32_REGS=0"
 #endif
 
+.global check_erratum_neoverse_n3_3699563
+
+add_erratum_entry neoverse_n3, ERRATUM(3699563), ERRATA_N3_3699563, NO_APPLY_AT_RESET
+
+check_erratum_ls neoverse_n3, ERRATUM(3699563), CPU_REV(0, 0)
+
 cpu_reset_func_start neoverse_n3
 	/* Disable speculative loads */
 	msr	SSBS, xzr

lib/cpus/cpu-ops.mk

@@ -733,6 +733,11 @@ CPU_FLAG_LIST += ERRATA_N2_2779511
 # of the Neoverse N2 cpu and is still open.
 CPU_FLAG_LIST += ERRATA_N2_3701773
 
+# Flag to apply erratum 3699563 workaround during context save/restore of
+# ICH_VMCR_EL2 reg. This erratum applies to revision r0p0 of the Neoverse N3
+# cpu and is still open.
+CPU_FLAG_LIST += ERRATA_N3_3699563
+
 # Flag to apply erratum 2002765 workaround during reset. This erratum applies
 # to revisions r0p0, r1p0, and r2p0 of the Cortex-X2 cpu and is still open.
 CPU_FLAG_LIST += ERRATA_X2_2002765

lib/cpus/errata_common.c

@@ -22,6 +22,7 @@
 #include <lib/cpus/cpu_ops.h>
 #include <lib/cpus/errata.h>
 #include <neoverse_n2.h>
+#include <neoverse_n3.h>
 
 #if ERRATA_A520_2938996 || ERRATA_X4_2726228
 unsigned int check_if_affected_core(void)
@@ -123,6 +124,12 @@ bool errata_ich_vmcr_el2_applies(void)
 		break;
 #endif /* ERRATA_N2_3701773 */
 
+#if ERRATA_N3_3699563
+	case EXTRACT_PARTNUM(NEOVERSE_N3_MIDR):
+		if (check_erratum_neoverse_n3_3699563(cpu_get_rev_var()) == ERRATA_APPLIES)
+			return true;
+		break;
+#endif /* ERRATA_N3_3699563 */
 	default:
 		break;
 	}