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ae6c7c97d4
Cortex-X2 erratum 3701772 that applies to r0p0, r1p0, r2p0, r2p1 is still Open. The workaround is for EL3 software that performs context save/restore on a change of Security state to use a value of SCR_EL3.NS when accessing ICH_VMCR_EL2 that reflects the Security state that owns the data being saved or restored. SDEN documentation: https://developer.arm.com/documentation/SDEN-1775100/latest/ Change-Id: I2ffc5e7d7467f1bcff8b895fea52a1daa7d14495 Signed-off-by: Govindraj Raja <govindraj.raja@arm.com>
71 lines
3.1 KiB
C
71 lines
3.1 KiB
C
/*
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* Copyright (c) 2021-2025, Arm Limited. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef CORTEX_X2_H
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#define CORTEX_X2_H
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#define CORTEX_X2_MIDR U(0x410FD480)
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/* Cortex-X2 loop count for CVE-2022-23960 mitigation */
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#define CORTEX_X2_BHB_LOOP_COUNT U(32)
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/*******************************************************************************
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* CPU Extended Control register specific definitions
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******************************************************************************/
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#define CORTEX_X2_CPUECTLR_EL1 S3_0_C15_C1_4
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#define CORTEX_X2_CPUECTLR_EL1_PFSTIDIS_BIT (ULL(1) << 8)
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/*******************************************************************************
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* CPU Extended Control register 2 specific definitions
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******************************************************************************/
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#define CORTEX_X2_CPUECTLR2_EL1 S3_0_C15_C1_5
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#define CORTEX_X2_CPUECTLR2_EL1_PF_MODE_SHIFT U(11)
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#define CORTEX_X2_CPUECTLR2_EL1_PF_MODE_WIDTH U(4)
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#define CORTEX_X2_CPUECTLR2_EL1_PF_MODE_CNSRV ULL(0x9)
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/*******************************************************************************
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* CPU Auxiliary Control register 3 specific definitions.
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******************************************************************************/
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#define CORTEX_X2_CPUACTLR3_EL1 S3_0_C15_C1_2
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/*******************************************************************************
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* CPU Power Control register specific definitions
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******************************************************************************/
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#define CORTEX_X2_CPUPWRCTLR_EL1 S3_0_C15_C2_7
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#define CORTEX_X2_CPUPWRCTLR_EL1_CORE_PWRDN_BIT U(1)
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/*******************************************************************************
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* CPU Auxiliary Control Register definitions
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******************************************************************************/
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#define CORTEX_X2_CPUACTLR_EL1 S3_0_C15_C1_0
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#define CORTEX_X2_CPUACTLR_EL1_BIT_22 (ULL(1) << 22)
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/*******************************************************************************
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* CPU Auxiliary Control Register 2 definitions
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******************************************************************************/
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#define CORTEX_X2_CPUACTLR2_EL1 S3_0_C15_C1_1
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#define CORTEX_X2_CPUACTLR2_EL1_BIT_40 (ULL(1) << 40)
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/*******************************************************************************
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* CPU Auxiliary Control Register 5 definitions
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******************************************************************************/
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#define CORTEX_X2_CPUACTLR5_EL1 S3_0_C15_C8_0
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#define CORTEX_X2_CPUACTLR5_EL1_BIT_17 (ULL(1) << 17)
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/*******************************************************************************
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* CPU Implementation Specific Selected Instruction registers
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******************************************************************************/
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#define CORTEX_X2_IMP_CPUPSELR_EL3 S3_6_C15_C8_0
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#define CORTEX_X2_IMP_CPUPCR_EL3 S3_6_C15_C8_1
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#define CORTEX_X2_IMP_CPUPOR_EL3 S3_6_C15_C8_2
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#define CORTEX_X2_IMP_CPUPMR_EL3 S3_6_C15_C8_3
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#ifndef __ASSEMBLER__
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long check_erratum_cortex_x2_3701772(long cpu_rev);
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#endif /* __ASSEMBLER__ */
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#endif /* CORTEX_X2_H */
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