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38401c5388
Cortex-X4 erratum 3701758 that applies to r0p0, r0p1, r0p2 and r0p3 is still Open. The workaround is for EL3 software that performs context save/restore on a change of Security state to use a value of SCR_EL3.NS when accessing ICH_VMCR_EL2 that reflects the Security state that owns the data being saved or restored. SDEN documentation: https://developer.arm.com/documentation/109148/latest/ Change-Id: I4ee941d1e7653de7a12d69f538ca05f7f9f9961d Signed-off-by: Govindraj Raja <govindraj.raja@arm.com>
57 lines
2.1 KiB
C
57 lines
2.1 KiB
C
/*
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* Copyright (c) 2022-2025, Arm Limited. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef CORTEX_X4_H
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#define CORTEX_X4_H
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#define CORTEX_X4_MIDR U(0x410FD821)
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/* Cortex X4 loop count for CVE-2022-23960 mitigation */
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#define CORTEX_X4_BHB_LOOP_COUNT U(132)
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/*******************************************************************************
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* CPU Extended Control register specific definitions
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******************************************************************************/
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#define CORTEX_X4_CPUECTLR_EL1 S3_0_C15_C1_4
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/*******************************************************************************
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* CPU Power Control register specific definitions
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******************************************************************************/
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#define CORTEX_X4_CPUPWRCTLR_EL1 S3_0_C15_C2_7
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#define CORTEX_X4_CPUPWRCTLR_EL1_CORE_PWRDN_BIT U(1)
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/*******************************************************************************
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* CPU Auxiliary control register specific definitions
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******************************************************************************/
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#define CORTEX_X4_CPUACTLR_EL1 S3_0_C15_C1_0
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#define CORTEX_X4_CPUACTLR3_EL1 S3_0_C15_C1_2
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#define CORTEX_X4_CPUACTLR4_EL1 S3_0_C15_C1_3
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/*******************************************************************************
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* CPU Auxiliary control register 5 specific definitions
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******************************************************************************/
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#define CORTEX_X4_CPUACTLR5_EL1 S3_0_C15_C8_0
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#define CORTEX_X4_CPUACTLR5_EL1_BIT_14 (ULL(1) << 14)
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/*******************************************************************************
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* CPU Auxiliary control register 6 specific definitions
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******************************************************************************/
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#define CORTEX_X4_CPUACTLR6_EL1 S3_0_C15_C8_1
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#ifndef __ASSEMBLER__
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#if ERRATA_X4_2726228
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long check_erratum_cortex_x4_2726228(long cpu_rev);
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#else
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static inline long check_erratum_cortex_x4_2726228(long cpu_rev)
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{
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return 0;
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}
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#endif /* ERRATA_X4_2726228 */
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long check_erratum_cortex_x4_3701758(long cpu_rev);
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#endif /* __ASSEMBLER__ */
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#endif /* CORTEX_X4_H */
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