fix(cpus): workaround for Cortex-X4 erratum 3701758

Cortex-X4 erratum 3701758 that applies to r0p0, r0p1, r0p2 and r0p3
is still Open.

The workaround is for EL3 software that performs context save/restore
on a change of Security state to use a value of SCR_EL3.NS when
accessing ICH_VMCR_EL2 that reflects the Security state that owns the
data being saved or restored.

SDEN documentation:
https://developer.arm.com/documentation/109148/latest/

Change-Id: I4ee941d1e7653de7a12d69f538ca05f7f9f9961d
Signed-off-by: Govindraj Raja <govindraj.raja@arm.com>

docs/design/cpu-specific-build-macros.rst

@@ -870,6 +870,10 @@ For Cortex-X4, the following errata build flags are defined :
 - ``ERRATA_X4_3076789``: This applies errata 3076789 workaround to Cortex-X4
   CPU. This needs to be enabled for revisions r0p0 and r0p1. It is fixed in r0p2.
 
+- ``ERRATA_X4_3701758``: This applies errata 3701758 workaround to Cortex-X4
+  CPU. This needs to be enabled for revisions r0p0, r0p1, r0p2 and r0p3.
+  It is still open.
+
 For Cortex-A510, the following errata build flags are defined :
 
 -  ``ERRATA_A510_1922240``: This applies errata 1922240 workaround to

include/lib/cpus/aarch64/cortex_x4.h

@@ -50,6 +50,8 @@ static inline long check_erratum_cortex_x4_2726228(long cpu_rev)
        return 0;
 }
 #endif /* ERRATA_X4_2726228 */
+
+long check_erratum_cortex_x4_3701758(long cpu_rev);
 #endif /* __ASSEMBLER__ */
 
 #endif /* CORTEX_X4_H */

lib/cpus/aarch64/cortex_x4.S

@@ -23,6 +23,7 @@
 #endif
 
 .global check_erratum_cortex_x4_2726228
+.global check_erratum_cortex_x4_3701758
 
 #if WORKAROUND_CVE_2022_23960
         wa_cve_2022_23960_bhb_vector_table CORTEX_X4_BHB_LOOP_COUNT, cortex_x4
@@ -119,6 +120,10 @@ workaround_reset_end cortex_x4, CVE(2024, 7881)
 
 check_erratum_chosen cortex_x4, CVE(2024, 7881), WORKAROUND_CVE_2024_7881
 
+add_erratum_entry cortex_x4, ERRATUM(3701758), ERRATA_X4_3701758, NO_APPLY_AT_RESET
+
+check_erratum_ls cortex_x4, ERRATUM(3701758), CPU_REV(0, 3)
+
 cpu_reset_func_start cortex_x4
 	/* Disable speculative loads */
 	msr	SSBS, xzr

lib/cpus/cpu-ops.mk

@@ -874,6 +874,11 @@ CPU_FLAG_LIST += ERRATA_X4_2923985
 # to revisions r0p0 and r0p1 of the Cortex-X4 cpu. It is fixed in r0p2.
 CPU_FLAG_LIST += ERRATA_X4_3076789
 
+# Flag to apply erratum 3701758 workaround during context save/restore of
+# ICH_VMCR_EL2 reg. This erratum applies to revisions r0p0, r0p1, r0p2 and r0p3
+# of the Cortex-X4 cpu and is still open.
+CPU_FLAG_LIST += ERRATA_X4_3701758
+
 # Flag to apply erratum 1922240 workaround during reset. This erratum applies
 # to revision r0p0 of the Cortex-A510 cpu and is fixed in r0p1.
 CPU_FLAG_LIST += ERRATA_A510_1922240

lib/cpus/errata_common.c

@@ -100,6 +100,13 @@ bool errata_ich_vmcr_el2_applies(void)
 		break;
 #endif /* ERRATA_X3_3701769 */
 
+#if ERRATA_X4_3701758
+	case EXTRACT_PARTNUM(CORTEX_X4_MIDR):
+		if (check_erratum_cortex_x4_3701758(cpu_get_rev_var()) == ERRATA_APPLIES)
+			return true;
+		break;
+#endif /* ERRATA_X4_3701758 */
+
 	default:
 		break;
 	}