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050c4a38a3
Cortex-A720 erratum 3699561 that applies to all revisions <= r0p2 and is still Open. The workaround is for EL3 software that performs context save/restore on a change of Security state to use a value of SCR_EL3.NS when accessing ICH_VMCR_EL2 that reflects the Security state that owns the data being saved or restored. SDEN documentation: https://developer.arm.com/documentation/SDEN-2439421/latest/ Change-Id: I7ea3aaf3e7bf6b4f3648f6872e505a41247b14ba Signed-off-by: Govindraj Raja <govindraj.raja@arm.com>
45 lines
1.8 KiB
C
45 lines
1.8 KiB
C
/*
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* Copyright (c) 2021-2025, Arm Limited. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef CORTEX_A720_H
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#define CORTEX_A720_H
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#define CORTEX_A720_MIDR U(0x410FD810)
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/* Cortex A720 loop count for CVE-2022-23960 mitigation */
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#define CORTEX_A720_BHB_LOOP_COUNT U(132)
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/*******************************************************************************
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* CPU Auxiliary Control register 1 specific definitions.
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******************************************************************************/
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#define CORTEX_A720_CPUACTLR_EL1 S3_0_C15_C1_0
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/*******************************************************************************
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* CPU Auxiliary Control register 2 specific definitions.
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******************************************************************************/
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#define CORTEX_A720_CPUACTLR2_EL1 S3_0_C15_C1_1
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/*******************************************************************************
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* CPU Auxiliary Control register 4 specific definitions.
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******************************************************************************/
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#define CORTEX_A720_CPUACTLR4_EL1 S3_0_C15_C1_3
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/*******************************************************************************
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* CPU Extended Control register specific definitions
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******************************************************************************/
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#define CORTEX_A720_CPUECTLR_EL1 S3_0_C15_C1_4
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/*******************************************************************************
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* CPU Power Control register specific definitions
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******************************************************************************/
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#define CORTEX_A720_CPUPWRCTLR_EL1 S3_0_C15_C2_7
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#define CORTEX_A720_CPUPWRCTLR_EL1_CORE_PWRDN_BIT U(1)
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#ifndef __ASSEMBLER__
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long check_erratum_cortex_a720_3699561(long cpu_rev);
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#endif /* __ASSEMBLER__ */
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#endif /* CORTEX_A720_H */
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