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fix(security): add CVE-2024-7881 mitigation to Neoverse-V2

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This patch mitigates CVE-2024-7881 [1] by setting CPUACTLR6_EL1[41] to 1
for Neoverse-V2 CPU.

[1]: https://developer.arm.com/Arm%20Security%20Center/Arm%20CPU%20Vulnerability%20CVE-2024-7881

Signed-off-by: Arvind Ram Prakash <arvind.ramprakash@arm.com>
Change-Id: I129814eb3494b287fd76a3f7dbc50f76553b2565
This commit is contained in:
Arvind Ram Prakash 2024-09-06 12:20:38 -05:00
parent 520c2207b9
commit 56bb1d172c
2 changed files with 18 additions and 2 deletions
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7
include/lib/cpus/aarch64/neoverse_v2.h
View file

@ -1,5 +1,5 @@
/*
* Copyright (c) 2021-2023, Arm Limited. All rights reserved.
* Copyright (c) 2021-2025, Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@ -58,4 +58,9 @@
#define NEOVERSE_V2_CPUACTLR5_EL1_BIT_56 (ULL(1) << 56)
#define NEOVERSE_V2_CPUACTLR5_EL1_BIT_55 (ULL(1) << 55)
/*******************************************************************************
* CPU Auxiliary control register 6 specific definitions
******************************************************************************/
#define NEOVERSE_V2_CPUACTLR6_EL1 S3_0_C15_C8_1
#endif /* NEOVERSE_V2_H */

13
lib/cpus/aarch64/neoverse_v2.S
View file

@ -1,5 +1,5 @@
/*
* Copyright (c) 2021-2024, Arm Limited. All rights reserved.
* Copyright (c) 2021-2025, Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@ -97,6 +97,17 @@ check_erratum_chosen neoverse_v2, CVE(2022, 23960), WORKAROUND_CVE_2022_23960
wa_cve_2022_23960_bhb_vector_table NEOVERSE_V2_BHB_LOOP_COUNT, neoverse_v2
#endif /* WORKAROUND_CVE_2022_23960 */
workaround_reset_start neoverse_v2, CVE(2024, 7881), WORKAROUND_CVE_2024_7881
/* ---------------------------------
* Sets BIT41 of CPUACTLR6_EL1 which
* disables L1 Data cache prefetcher
* ---------------------------------
*/
sysreg_bit_set NEOVERSE_V2_CPUACTLR6_EL1, BIT(41)
workaround_reset_end neoverse_v2, CVE(2024, 7881)
check_erratum_chosen neoverse_v2, CVE(2024, 7881), WORKAROUND_CVE_2024_7881
/* ----------------------------------------------------
* HW will do the cache maintenance while powering down
* ----------------------------------------------------