diff --git a/include/lib/cpus/aarch64/neoverse_v2.h b/include/lib/cpus/aarch64/neoverse_v2.h index 1171e9523..427cafa86 100644 --- a/include/lib/cpus/aarch64/neoverse_v2.h +++ b/include/lib/cpus/aarch64/neoverse_v2.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2021-2023, Arm Limited. All rights reserved. + * Copyright (c) 2021-2025, Arm Limited. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -58,4 +58,9 @@ #define NEOVERSE_V2_CPUACTLR5_EL1_BIT_56 (ULL(1) << 56) #define NEOVERSE_V2_CPUACTLR5_EL1_BIT_55 (ULL(1) << 55) +/******************************************************************************* + * CPU Auxiliary control register 6 specific definitions + ******************************************************************************/ +#define NEOVERSE_V2_CPUACTLR6_EL1 S3_0_C15_C8_1 + #endif /* NEOVERSE_V2_H */ diff --git a/lib/cpus/aarch64/neoverse_v2.S b/lib/cpus/aarch64/neoverse_v2.S index f56a5e86d..56b512455 100644 --- a/lib/cpus/aarch64/neoverse_v2.S +++ b/lib/cpus/aarch64/neoverse_v2.S @@ -1,5 +1,5 @@ /* - * Copyright (c) 2021-2024, Arm Limited. All rights reserved. + * Copyright (c) 2021-2025, Arm Limited. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -97,6 +97,17 @@ check_erratum_chosen neoverse_v2, CVE(2022, 23960), WORKAROUND_CVE_2022_23960 wa_cve_2022_23960_bhb_vector_table NEOVERSE_V2_BHB_LOOP_COUNT, neoverse_v2 #endif /* WORKAROUND_CVE_2022_23960 */ +workaround_reset_start neoverse_v2, CVE(2024, 7881), WORKAROUND_CVE_2024_7881 + /* --------------------------------- + * Sets BIT41 of CPUACTLR6_EL1 which + * disables L1 Data cache prefetcher + * --------------------------------- + */ + sysreg_bit_set NEOVERSE_V2_CPUACTLR6_EL1, BIT(41) +workaround_reset_end neoverse_v2, CVE(2024, 7881) + +check_erratum_chosen neoverse_v2, CVE(2024, 7881), WORKAROUND_CVE_2024_7881 + /* ---------------------------------------------------- * HW will do the cache maintenance while powering down * ----------------------------------------------------