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a727d59d9c
Add Cortex-A35 l2 extended control register definition. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Change-Id: I14c766a88c95fef0f95a6f2e9d8ca87dbeac77c2
32 lines
1.1 KiB
C
32 lines
1.1 KiB
C
/*
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* Copyright (c) 2016-2024, Arm Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef CORTEX_A35_H
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#define CORTEX_A35_H
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#include <lib/utils_def.h>
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/* Cortex-A35 Main ID register for revision 0 */
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#define CORTEX_A35_MIDR U(0x410FD040)
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/* L2 Extended Control Register */
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#define CORTEX_A35_L2ECTLR_EL1 S3_1_C11_C0_3
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/*******************************************************************************
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* CPU Extended Control register specific definitions.
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* CPUECTLR_EL1 is an implementation-specific register.
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******************************************************************************/
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#define CORTEX_A35_CPUECTLR_EL1 S3_1_C15_C2_1
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#define CORTEX_A35_CPUECTLR_SMPEN_BIT (ULL(1) << 6)
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/*******************************************************************************
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* CPU Auxiliary Control register specific definitions.
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******************************************************************************/
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#define CORTEX_A35_CPUACTLR_EL1 S3_1_C15_C2_0
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#define CORTEX_A35_CPUACTLR_EL1_ENDCCASCI (ULL(1) << 44)
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#endif /* CORTEX_A35_H */
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