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fded839285
Neoverse-N3 erratum 3699563 that applies to r0p0 is still Open. The workaround is for EL3 software that performs context save/restore on a change of Security state to use a value of SCR_EL3.NS when accessing ICH_VMCR_EL2 that reflects the Security state that owns the data being saved or restored. SDEN documentation: https://developer.arm.com/documentation/SDEN-3050973/latest/ Change-Id: I77aaf8ae0afff3adde9a85f4a1a13ac9d1daf0af Signed-off-by: Govindraj Raja <govindraj.raja@arm.com>
28 lines
978 B
C
28 lines
978 B
C
/*
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* Copyright (c) 2023-2025, Arm Limited. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef NEOVERSE_N3_H
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#define NEOVERSE_N3_H
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#define NEOVERSE_N3_MIDR U(0x410FD8E0)
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/*******************************************************************************
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* CPU Extended Control register specific definitions
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******************************************************************************/
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#define NEOVERSE_N3_CPUECTLR_EL1 S3_0_C15_C1_4
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#define NEOVERSE_N3_CPUECTLR_EL1_EXTLLC_BIT (ULL(1) << 0)
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/*******************************************************************************
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* CPU Power Control register specific definitions
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******************************************************************************/
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#define NEOVERSE_N3_CPUPWRCTLR_EL1 S3_0_C15_C2_7
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#define NEOVERSE_N3_CPUPWRCTLR_EL1_CORE_PWRDN_BIT U(1)
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#ifndef __ASSEMBLER__
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long check_erratum_neoverse_n3_3699563(long cpu_rev);
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#endif /* __ASSEMBLER__ */
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#endif /* NEOVERSE_N3_H */
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