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perf(cpus): make reset errata do fewer branches
Errata application is painful for performance. For a start, it's done when the core has just come out of reset, which means branch predictors and caches will be empty so a branch to a workaround function must be fetched from memory and that round trip is very slow. Then it also runs with the I-cache off, which means that the loop to iterate over the workarounds must also be fetched from memory on each iteration. We can remove both branches. First, we can simply apply every erratum directly instead of defining a workaround function and jumping to it. Currently, no errata that need to be applied at both reset and runtime, with the same workaround function, exist. If the need arose in future, this should be achievable with a reset + runtime wrapper combo. Then, we can construct a function that applies each erratum linearly instead of looping over the list. If this function is part of the reset function, then the only "far" branches at reset will be for the checker functions. Importantly, this mitigates the slowdown even when an erratum is disabled. The result is ~50% speedup on N1SDP and ~20% on AArch64 Juno on wakeup from PSCI calls that end in powerdown. This is roughly back to the baseline of v2.9, before the errata framework regressed on performance (or a little better). It is important to note that there are other slowdowns since then that remain unknown. Change-Id: Ie4d5288a331b11fd648e5c4a0b652b74160b07b9 Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>
This commit is contained in:
Boyan Karatotev
parent
b07c317f67
commit
89dba82dfa
48 changed files with 185 additions and 126 deletions
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@ -1481,7 +1481,9 @@ the returned ``cpu_ops`` is then invoked which executes the required reset
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handling for that CPU and also any errata workarounds enabled by the platform.
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It should be defined using the ``cpu_reset_func_{start,end}`` macros and its
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body may only clobber x0 to x14 with x14 being the cpu_rev parameter.
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body may only clobber x0 to x14 with x14 being the cpu_rev parameter. The cpu
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file should also include a call to ``cpu_reset_prologue`` at the start of the
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file for errata to work correctly.
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CPU specific power down sequence
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~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
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@ -172,11 +172,6 @@
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\_cpu\()_errata_list_start:
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.endif
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/* unused on AArch32, maintain for portability */
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.word 0
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/* TODO(errata ABI): this prevents all checker functions from
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* being optimised away. Can be done away with unless the ABI
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* needs them */
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.ifnb \_special
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.word check_errata_\_special
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.elseif \_cve
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@ -188,9 +183,7 @@
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.word \_id
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.hword \_cve
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.byte \_chosen
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/* TODO(errata ABI): mitigated field for known but unmitigated
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* errata*/
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.byte 0x1
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.byte 0x0 /* alignment */
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.popsection
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.endm
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@ -238,50 +238,22 @@
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* _apply_at_reset:
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* Whether the erratum should be automatically applied at reset
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*/
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.macro add_erratum_entry _cpu:req, _cve:req, _id:req, _chosen:req, _apply_at_reset:req
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.macro add_erratum_entry _cpu:req, _cve:req, _id:req, _chosen:req
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#if REPORT_ERRATA || ERRATA_ABI_SUPPORT
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.pushsection .rodata.errata_entries
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.align 3
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.ifndef \_cpu\()_errata_list_start
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\_cpu\()_errata_list_start:
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.endif
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/* check if unused and compile out if no references */
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.if \_apply_at_reset && \_chosen
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.quad erratum_\_cpu\()_\_id\()_wa
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.else
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.quad 0
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.endif
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/* TODO(errata ABI): this prevents all checker functions from
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* being optimised away. Can be done away with unless the ABI
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* needs them */
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.quad check_erratum_\_cpu\()_\_id
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/* Will fit CVEs with up to 10 character in the ID field */
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.word \_id
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.hword \_cve
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.byte \_chosen
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/* TODO(errata ABI): mitigated field for known but unmitigated
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* errata */
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.byte 0x1
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.byte 0x0 /* alignment */
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.popsection
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.endm
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.macro _workaround_start _cpu:req, _cve:req, _id:req, _chosen:req, _apply_at_reset:req
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add_erratum_entry \_cpu, \_cve, \_id, \_chosen, \_apply_at_reset
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func erratum_\_cpu\()_\_id\()_wa
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mov x8, x30
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/* save rev_var for workarounds that might need it but don't
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* restore to x0 because few will care */
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mov x7, x0
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bl check_erratum_\_cpu\()_\_id
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cbz x0, erratum_\_cpu\()_\_id\()_skip
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.endm
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.macro _workaround_end _cpu:req, _id:req
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erratum_\_cpu\()_\_id\()_skip:
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ret x8
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endfunc erratum_\_cpu\()_\_id\()_wa
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#endif
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.endm
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/*******************************************************************************
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@ -311,7 +283,22 @@
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* _wa clobbers: x0-x8 (PCS compliant)
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*/
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.macro workaround_reset_start _cpu:req, _cve:req, _id:req, _chosen:req
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_workaround_start \_cpu, \_cve, \_id, \_chosen, 1
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add_erratum_entry \_cpu, \_cve, \_id, \_chosen
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.if \_chosen
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/* put errata directly into the reset function */
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.pushsection .text.asm.\_cpu\()_reset_func, "ax"
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.else
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/* or something else that will get garbage collected by the
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* linker */
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.pushsection .text.asm.erratum_\_cpu\()_\_id\()_wa, "ax"
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.endif
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/* revision is stored in x14, get it */
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mov x0, x14
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bl check_erratum_\_cpu\()_\_id
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/* save rev_var for workarounds that might need it */
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mov x7, x14
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cbz x0, erratum_\_cpu\()_\_id\()_skip_reset
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.endm
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/*
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@ -322,6 +309,10 @@
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* for errata applied in generic code
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*/
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.macro workaround_runtime_start _cpu:req, _cve:req, _id:req, _chosen:req, _midr
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add_erratum_entry \_cpu, \_cve, \_id, \_chosen
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func erratum_\_cpu\()_\_id\()_wa
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mov x8, x30
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/*
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* Let errata specify if they need MIDR checking. Sadly, storing the
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* MIDR in an .equ to retrieve automatically blows up as it stores some
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@ -329,11 +320,15 @@
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*/
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.ifnb \_midr
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jump_if_cpu_midr \_midr, 1f
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b erratum_\_cpu\()_\_id\()_skip
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b erratum_\_cpu\()_\_id\()_skip_runtime
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1:
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.endif
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_workaround_start \_cpu, \_cve, \_id, \_chosen, 0
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/* save rev_var for workarounds that might need it but don't
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* restore to x0 because few will care */
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mov x7, x0
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bl check_erratum_\_cpu\()_\_id
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cbz x0, erratum_\_cpu\()_\_id\()_skip_runtime
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.endm
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/*
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@ -341,7 +336,8 @@
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* is kept here so the same #define can be used as that macro
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*/
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.macro workaround_reset_end _cpu:req, _cve:req, _id:req
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_workaround_end \_cpu, \_id
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erratum_\_cpu\()_\_id\()_skip_reset:
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.popsection
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.endm
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/*
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@ -361,7 +357,9 @@
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.ifb \_no_isb
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isb
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.endif
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_workaround_end \_cpu, \_id
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erratum_\_cpu\()_\_id\()_skip_runtime:
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ret x8
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endfunc erratum_\_cpu\()_\_id\()_wa
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.endm
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/*******************************************************************************
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@ -598,7 +596,21 @@
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******************************************************************************/
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/*
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* Wrapper to automatically apply all reset-time errata. Will end with an isb.
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* Helper to register a cpu with the errata framework. Begins the definition of
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* the reset function.
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*
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* _cpu:
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* Name of cpu as given to declare_cpu_ops
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*/
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.macro cpu_reset_prologue _cpu:req
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func \_cpu\()_reset_func
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mov x15, x30
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get_rev_var x14, x0
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.endm
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/*
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* Wrapper of the reset function to automatically apply all reset-time errata.
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* Will end with an isb.
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*
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* _cpu:
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* Name of cpu as given to declare_cpu_ops
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@ -608,38 +620,9 @@
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* argument x14 - cpu_rev_var
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*/
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.macro cpu_reset_func_start _cpu:req
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func \_cpu\()_reset_func
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mov x15, x30
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get_rev_var x14, x0
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/* short circuit the location to avoid searching the list */
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adrp x12, \_cpu\()_errata_list_start
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add x12, x12, :lo12:\_cpu\()_errata_list_start
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adrp x13, \_cpu\()_errata_list_end
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add x13, x13, :lo12:\_cpu\()_errata_list_end
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errata_begin:
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/* if head catches up with end of list, exit */
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cmp x12, x13
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b.eq errata_end
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ldr x10, [x12, #ERRATUM_WA_FUNC]
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/* TODO(errata ABI): check mitigated and checker function fields
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* for 0 */
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ldrb w11, [x12, #ERRATUM_CHOSEN]
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/* skip if not chosen */
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cbz x11, 1f
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/* skip if runtime erratum */
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cbz x10, 1f
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/* put cpu revision in x0 and call workaround */
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mov x0, x14
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blr x10
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1:
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add x12, x12, #ERRATUM_ENTRY_SIZE
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b errata_begin
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errata_end:
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/* the func/endfunc macros will change sections. So change the section
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* back to the reset function's */
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.section .text.asm.\_cpu\()_reset_func, "ax"
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.endm
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.macro cpu_reset_func_end _cpu:req
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@ -9,20 +9,18 @@
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#include <lib/cpus/cpu_ops.h>
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#define ERRATUM_WA_FUNC_SIZE CPU_WORD_SIZE
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#define ERRATUM_CHECK_FUNC_SIZE CPU_WORD_SIZE
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#define ERRATUM_ID_SIZE 4
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#define ERRATUM_CVE_SIZE 2
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#define ERRATUM_CHOSEN_SIZE 1
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#define ERRATUM_MITIGATED_SIZE 1
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#define ERRATUM_ALIGNMENT_SIZE 1
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#define ERRATUM_WA_FUNC 0
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#define ERRATUM_CHECK_FUNC ERRATUM_WA_FUNC + ERRATUM_WA_FUNC_SIZE
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#define ERRATUM_CHECK_FUNC 0
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#define ERRATUM_ID ERRATUM_CHECK_FUNC + ERRATUM_CHECK_FUNC_SIZE
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#define ERRATUM_CVE ERRATUM_ID + ERRATUM_ID_SIZE
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#define ERRATUM_CHOSEN ERRATUM_CVE + ERRATUM_CVE_SIZE
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#define ERRATUM_MITIGATED ERRATUM_CHOSEN + ERRATUM_CHOSEN_SIZE
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#define ERRATUM_ENTRY_SIZE ERRATUM_MITIGATED + ERRATUM_MITIGATED_SIZE
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#define ERRATUM_ALIGNMENT ERRATUM_CHOSEN + ERRATUM_CHOSEN_SIZE
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#define ERRATUM_ENTRY_SIZE ERRATUM_ALIGNMENT + ERRATUM_ALIGNMENT_SIZE
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/* Errata status */
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#define ERRATA_NOT_APPLIES 0
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@ -39,15 +37,13 @@ void print_errata_status(void);
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* uintptr_t will reflect the change and the alignment will be correct in both.
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*/
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struct erratum_entry {
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uintptr_t (*wa_func)(uint64_t cpu_rev);
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uintptr_t (*check_func)(uint64_t cpu_rev);
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/* Will fit CVEs with up to 10 character in the ID field */
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uint32_t id;
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/* Denote CVEs with their year or errata with 0 */
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uint16_t cve;
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uint8_t chosen;
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/* TODO(errata ABI): placeholder for the mitigated field */
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uint8_t _mitigated;
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uint8_t _alignment;
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} __packed;
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CASSERT(sizeof(struct erratum_entry) == ERRATUM_ENTRY_SIZE,
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@ -8,6 +8,8 @@
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#include <asm_macros.S>
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#include <cpu_macros.S>
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cpu_reset_prologue aem_generic
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func aem_generic_core_pwr_dwn
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/* ---------------------------------------------
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* Disable the Data Cache.
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@ -1,5 +1,5 @@
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/*
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* Copyright (c) 2016-2024, Arm Limited and Contributors. All rights reserved.
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* Copyright (c) 2016-2025, Arm Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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@ -11,6 +11,7 @@
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#include <cpu_macros.S>
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#include <plat_macros.S>
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cpu_reset_prologue cortex_a35
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/* ---------------------------------------------
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* Disable L1 data cache and unified L2 cache
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* ---------------------------------------------
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@ -22,6 +22,8 @@
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#error "Cortex-A510 supports only AArch64. Compile with CTX_INCLUDE_AARCH32_REGS=0"
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#endif
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cpu_reset_prologue cortex_a510
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workaround_reset_start cortex_a510, ERRATUM(1922240), ERRATA_A510_1922240
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/* Apply the workaround by setting IMP_CMPXACTLR_EL1[11:10] = 0b11. */
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sysreg_bitfield_insert CORTEX_A510_CMPXACTLR_EL1, CORTEX_A510_CMPXACTLR_EL1_SNPPREFERUNIQUE_DISABLE, \
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@ -24,6 +24,8 @@
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#error "Cortex A520 supports only AArch64. Compile with CTX_INCLUDE_AARCH32_REGS=0"
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#endif
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cpu_reset_prologue cortex_a520
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workaround_reset_start cortex_a520, ERRATUM(2630792), ERRATA_A520_2630792
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sysreg_bit_set CORTEX_A520_CPUACTLR_EL1, BIT(38)
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workaround_reset_end cortex_a520, ERRATUM(2630792)
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@ -1,5 +1,5 @@
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/*
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* Copyright (c) 2014-2024, Arm Limited and Contributors. All rights reserved.
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* Copyright (c) 2014-2025, Arm Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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@ -12,6 +12,8 @@
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#include <plat_macros.S>
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#include <lib/cpus/errata.h>
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cpu_reset_prologue cortex_a53
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/* ---------------------------------------------
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* Disable L1 data cache and unified L2 cache
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* ---------------------------------------------
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@ -36,12 +38,12 @@ endfunc cortex_a53_disable_smp
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/* Due to the nature of the errata it is applied unconditionally when chosen */
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check_erratum_ls cortex_a53, ERRATUM(819472), CPU_REV(0, 1)
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/* erratum workaround is interleaved with generic code */
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add_erratum_entry cortex_a53, ERRATUM(819472), ERRATUM_ALWAYS_CHOSEN, NO_APPLY_AT_RESET
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add_erratum_entry cortex_a53, ERRATUM(819472), ERRATUM_ALWAYS_CHOSEN
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/* Due to the nature of the errata it is applied unconditionally when chosen */
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check_erratum_ls cortex_a53, ERRATUM(824069), CPU_REV(0, 2)
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/* erratum workaround is interleaved with generic code */
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add_erratum_entry cortex_a53, ERRATUM(824069), ERRATUM_ALWAYS_CHOSEN, NO_APPLY_AT_RESET
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add_erratum_entry cortex_a53, ERRATUM(824069), ERRATUM_ALWAYS_CHOSEN
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workaround_reset_start cortex_a53, ERRATUM(826319), ERRATA_A53_826319
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mrs x1, CORTEX_A53_L2ACTLR_EL1
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@ -55,7 +57,7 @@ check_erratum_ls cortex_a53, ERRATUM(826319), CPU_REV(0, 2)
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/* Due to the nature of the errata it is applied unconditionally when chosen */
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check_erratum_ls cortex_a53, ERRATUM(827319), CPU_REV(0, 2)
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/* erratum workaround is interleaved with generic code */
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add_erratum_entry cortex_a53, ERRATUM(827319), ERRATUM_ALWAYS_CHOSEN, NO_APPLY_AT_RESET
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add_erratum_entry cortex_a53, ERRATUM(827319), ERRATUM_ALWAYS_CHOSEN
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check_erratum_custom_start cortex_a53, ERRATUM(835769)
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cmp x0, CPU_REV(0, 4)
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@ -78,7 +80,7 @@ exit_check_errata_835769:
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check_erratum_custom_end cortex_a53, ERRATUM(835769)
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/* workaround at build time */
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add_erratum_entry cortex_a53, ERRATUM(835769), ERRATA_A53_835769, NO_APPLY_AT_RESET
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add_erratum_entry cortex_a53, ERRATUM(835769), ERRATA_A53_835769
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/*
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* Disable the cache non-temporal hint.
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@ -114,7 +116,7 @@ exit_check_errata_843419:
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check_erratum_custom_end cortex_a53, ERRATUM(843419)
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/* workaround at build time */
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add_erratum_entry cortex_a53, ERRATUM(843419), ERRATA_A53_843419, NO_APPLY_AT_RESET
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add_erratum_entry cortex_a53, ERRATUM(843419), ERRATA_A53_843419
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/*
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* Earlier revisions of the core are affected as well, but don't
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@ -131,7 +133,7 @@ check_erratum_hs cortex_a53, ERRATUM(855873), CPU_REV(0, 3)
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check_erratum_chosen cortex_a53, ERRATUM(1530924), ERRATA_A53_1530924
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/* erratum has no workaround in the cpu. Generic code must take care */
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add_erratum_entry cortex_a53, ERRATUM(1530924), ERRATA_A53_1530924, NO_APPLY_AT_RESET
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add_erratum_entry cortex_a53, ERRATUM(1530924), ERRATA_A53_1530924
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cpu_reset_func_start cortex_a53
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/* Enable the SMP bit. */
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@ -20,6 +20,8 @@
|
|||
.globl cortex_a55_reset_func
|
||||
.globl cortex_a55_core_pwr_dwn
|
||||
|
||||
cpu_reset_prologue cortex_a55
|
||||
|
||||
workaround_reset_start cortex_a55, ERRATUM(798953), ERRATA_DSU_798953
|
||||
errata_dsu_798953_wa_impl
|
||||
workaround_reset_end cortex_a55, ERRATUM(798953)
|
||||
|
|
@ -111,7 +113,7 @@ check_erratum_ls cortex_a55, ERRATUM(1221012), CPU_REV(1, 0)
|
|||
check_erratum_chosen cortex_a55, ERRATUM(1530923), ERRATA_A55_1530923
|
||||
|
||||
/* erratum has no workaround in the cpu. Generic code must take care */
|
||||
add_erratum_entry cortex_a55, ERRATUM(1530923), ERRATA_A55_1530923, NO_APPLY_AT_RESET
|
||||
add_erratum_entry cortex_a55, ERRATUM(1530923), ERRATA_A55_1530923
|
||||
|
||||
cpu_reset_func_start cortex_a55
|
||||
cpu_reset_func_end cortex_a55
|
||||
|
|
|
|||
|
|
@ -13,6 +13,8 @@
|
|||
#include <cpu_macros.S>
|
||||
#include <plat_macros.S>
|
||||
|
||||
cpu_reset_prologue cortex_a57
|
||||
|
||||
/* ---------------------------------------------
|
||||
* Disable L1 data cache and unified L2 cache
|
||||
* ---------------------------------------------
|
||||
|
|
@ -81,7 +83,7 @@ check_erratum_ls cortex_a57, ERRATUM(806969), CPU_REV(0, 0)
|
|||
|
||||
/* erratum always worked around, but report it correctly */
|
||||
check_erratum_ls cortex_a57, ERRATUM(813419), CPU_REV(0, 0)
|
||||
add_erratum_entry cortex_a57, ERRATUM(813419), ERRATUM_ALWAYS_CHOSEN, NO_APPLY_AT_RESET
|
||||
add_erratum_entry cortex_a57, ERRATUM(813419), ERRATUM_ALWAYS_CHOSEN
|
||||
|
||||
workaround_reset_start cortex_a57, ERRATUM(813420), ERRATA_A57_813420
|
||||
sysreg_bit_set CORTEX_A57_CPUACTLR_EL1, CORTEX_A57_CPUACTLR_EL1_DCC_AS_DCCI
|
||||
|
|
@ -150,7 +152,7 @@ check_erratum_ls cortex_a57, ERRATUM(859972), CPU_REV(1, 3)
|
|||
|
||||
check_erratum_chosen cortex_a57, ERRATUM(1319537), ERRATA_A57_1319537
|
||||
/* erratum has no workaround in the cpu. Generic code must take care */
|
||||
add_erratum_entry cortex_a57, ERRATUM(1319537), ERRATA_A57_1319537, NO_APPLY_AT_RESET
|
||||
add_erratum_entry cortex_a57, ERRATUM(1319537), ERRATA_A57_1319537
|
||||
|
||||
workaround_reset_start cortex_a57, CVE(2017, 5715), WORKAROUND_CVE_2017_5715
|
||||
#if IMAGE_BL31
|
||||
|
|
|
|||
|
|
@ -23,6 +23,8 @@
|
|||
#error "Cortex-A65 supports only AArch64. Compile with CTX_INCLUDE_AARCH32_REGS=0"
|
||||
#endif
|
||||
|
||||
cpu_reset_prologue cortex_a65
|
||||
|
||||
workaround_reset_start cortex_a65, ERRATUM(936184), ERRATA_DSU_936184
|
||||
errata_dsu_936184_wa_impl
|
||||
workaround_reset_end cortex_a65, ERRATUM(936184)
|
||||
|
|
|
|||
|
|
@ -23,6 +23,8 @@
|
|||
#error "Cortex-A65AE supports only AArch64. Compile with CTX_INCLUDE_AARCH32_REGS=0"
|
||||
#endif
|
||||
|
||||
cpu_reset_prologue cortex_a65ae
|
||||
|
||||
workaround_reset_start cortex_a65ae, ERRATUM(936184), ERRATA_DSU_936184
|
||||
errata_dsu_936184_wa_impl
|
||||
workaround_reset_end cortex_a65ae, ERRATUM(936184)
|
||||
|
|
|
|||
|
|
@ -29,6 +29,8 @@
|
|||
wa_cve_2022_23960_bhb_vector_table CORTEX_A710_BHB_LOOP_COUNT, cortex_a710
|
||||
#endif /* WORKAROUND_CVE_2022_23960 */
|
||||
|
||||
cpu_reset_prologue cortex_a710
|
||||
|
||||
/* Disable hardware page aggregation. Enables mitigation for `CVE-2024-5660` */
|
||||
workaround_reset_start cortex_a710, CVE(2024, 5660), WORKAROUND_CVE_2024_5660
|
||||
sysreg_bit_set CORTEX_A710_CPUECTLR_EL1, BIT(46)
|
||||
|
|
@ -223,7 +225,7 @@ workaround_reset_end cortex_a710, CVE(2022, 23960)
|
|||
|
||||
check_erratum_chosen cortex_a710, CVE(2022, 23960), WORKAROUND_CVE_2022_23960
|
||||
|
||||
add_erratum_entry cortex_a710, ERRATUM(3701772), ERRATA_A710_3701772, NO_APPLY_AT_RESET
|
||||
add_erratum_entry cortex_a710, ERRATUM(3701772), ERRATA_A710_3701772
|
||||
|
||||
check_erratum_ls cortex_a710, ERRATUM(3701772), CPU_REV(2, 1)
|
||||
|
||||
|
|
|
|||
|
|
@ -28,6 +28,8 @@
|
|||
wa_cve_2022_23960_bhb_vector_table CORTEX_A715_BHB_LOOP_COUNT, cortex_a715
|
||||
#endif /* WORKAROUND_CVE_2022_23960 */
|
||||
|
||||
cpu_reset_prologue cortex_a715
|
||||
|
||||
workaround_reset_start cortex_a715, ERRATUM(2331818), ERRATA_A715_2331818
|
||||
sysreg_bit_set CORTEX_A715_CPUACTLR2_EL1, BIT(20)
|
||||
workaround_reset_end cortex_a715, ERRATUM(2331818)
|
||||
|
|
@ -129,7 +131,7 @@ workaround_reset_end cortex_a715, CVE(2022, 23960)
|
|||
|
||||
check_erratum_chosen cortex_a715, CVE(2022, 23960), WORKAROUND_CVE_2022_23960
|
||||
|
||||
add_erratum_entry cortex_a715, ERRATUM(3699560), ERRATA_A715_3699560, NO_APPLY_AT_RESET
|
||||
add_erratum_entry cortex_a715, ERRATUM(3699560), ERRATA_A715_3699560
|
||||
|
||||
check_erratum_ls cortex_a715, ERRATUM(3699560), CPU_REV(1, 3)
|
||||
|
||||
|
|
|
|||
|
|
@ -1,5 +1,5 @@
|
|||
/*
|
||||
* Copyright (c) 2015-2024, Arm Limited and Contributors. All rights reserved.
|
||||
* Copyright (c) 2015-2025, Arm Limited and Contributors. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
|
@ -15,6 +15,8 @@
|
|||
wa_cve_2022_23960_bhb_vector_table CORTEX_A72_BHB_LOOP_COUNT, cortex_a72
|
||||
#endif /* WORKAROUND_CVE_2022_23960 */
|
||||
|
||||
cpu_reset_prologue cortex_a72
|
||||
|
||||
/* ---------------------------------------------
|
||||
* Disable L1 data cache and unified L2 cache
|
||||
* ---------------------------------------------
|
||||
|
|
@ -92,7 +94,7 @@ check_erratum_ls cortex_a72, ERRATUM(859971), CPU_REV(0, 3)
|
|||
/* Due to the nature of the errata it is applied unconditionally when chosen */
|
||||
check_erratum_chosen cortex_a72, ERRATUM(1319367), ERRATA_A72_1319367
|
||||
/* erratum workaround is interleaved with generic code */
|
||||
add_erratum_entry cortex_a72, ERRATUM(1319367), ERRATA_A72_1319367, NO_APPLY_AT_RESET
|
||||
add_erratum_entry cortex_a72, ERRATUM(1319367), ERRATA_A72_1319367
|
||||
|
||||
workaround_reset_start cortex_a72, CVE(2017, 5715), WORKAROUND_CVE_2017_5715
|
||||
#if IMAGE_BL31
|
||||
|
|
|
|||
|
|
@ -22,6 +22,8 @@
|
|||
#error "Cortex A720 supports only AArch64. Compile with CTX_INCLUDE_AARCH32_REGS=0"
|
||||
#endif
|
||||
|
||||
cpu_reset_prologue cortex_a720
|
||||
|
||||
.global check_erratum_cortex_a720_3699561
|
||||
|
||||
#if WORKAROUND_CVE_2022_23960
|
||||
|
|
@ -74,7 +76,7 @@ workaround_reset_end cortex_a720, CVE(2022, 23960)
|
|||
|
||||
check_erratum_chosen cortex_a720, CVE(2022, 23960), WORKAROUND_CVE_2022_23960
|
||||
|
||||
add_erratum_entry cortex_a720, ERRATUM(3699561), ERRATA_A720_3699561, NO_APPLY_AT_RESET
|
||||
add_erratum_entry cortex_a720, ERRATUM(3699561), ERRATA_A720_3699561
|
||||
|
||||
check_erratum_ls cortex_a720, ERRATUM(3699561), CPU_REV(0, 2)
|
||||
|
||||
|
|
|
|||
|
|
@ -21,9 +21,11 @@
|
|||
#error "Cortex-A720AE supports only AArch64. Compile with CTX_INCLUDE_AARCH32_REGS=0"
|
||||
#endif
|
||||
|
||||
cpu_reset_prologue cortex_a720_ae
|
||||
|
||||
.global check_erratum_cortex_a720_ae_3699562
|
||||
|
||||
add_erratum_entry cortex_a720_ae, ERRATUM(3699562), ERRATA_A720_AE_3699562, NO_APPLY_AT_RESET
|
||||
add_erratum_entry cortex_a720_ae, ERRATUM(3699562), ERRATA_A720_AE_3699562
|
||||
|
||||
check_erratum_ls cortex_a720_ae, ERRATUM(3699562), CPU_REV(0, 0)
|
||||
|
||||
|
|
|
|||
|
|
@ -21,9 +21,11 @@
|
|||
#error "Cortex-A725 supports only AArch64. Compile with CTX_INCLUDE_AARCH32_REGS=0"
|
||||
#endif
|
||||
|
||||
cpu_reset_prologue cortex_a725
|
||||
|
||||
.global check_erratum_cortex_a725_3699564
|
||||
|
||||
add_erratum_entry cortex_a725, ERRATUM(3699564), ERRATA_A725_3699564, NO_APPLY_AT_RESET
|
||||
add_erratum_entry cortex_a725, ERRATUM(3699564), ERRATA_A725_3699564
|
||||
|
||||
check_erratum_ls cortex_a725, ERRATUM(3699564), CPU_REV(0, 1)
|
||||
|
||||
|
|
|
|||
|
|
@ -1,5 +1,5 @@
|
|||
/*
|
||||
* Copyright (c) 2016-2024, Arm Limited and Contributors. All rights reserved.
|
||||
* Copyright (c) 2016-2025, Arm Limited and Contributors. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
|
@ -10,6 +10,8 @@
|
|||
#include <cpu_macros.S>
|
||||
#include <plat_macros.S>
|
||||
|
||||
cpu_reset_prologue cortex_a73
|
||||
|
||||
/* ---------------------------------------------
|
||||
* Disable L1 data cache
|
||||
* ---------------------------------------------
|
||||
|
|
|
|||
|
|
@ -18,6 +18,8 @@
|
|||
#error "Cortex-A75 must be compiled with HW_ASSISTED_COHERENCY enabled"
|
||||
#endif
|
||||
|
||||
cpu_reset_prologue cortex_a75
|
||||
|
||||
workaround_reset_start cortex_a75, ERRATUM(764081), ERRATA_A75_764081
|
||||
sysreg_bit_set sctlr_el3, SCTLR_IESB_BIT
|
||||
workaround_reset_end cortex_a75, ERRATUM(764081)
|
||||
|
|
|
|||
|
|
@ -30,6 +30,8 @@
|
|||
#define ESR_EL3_A64_SMC0 0x5e000000
|
||||
#define ESR_EL3_A32_SMC0 0x4e000000
|
||||
|
||||
cpu_reset_prologue cortex_a76
|
||||
|
||||
#if DYNAMIC_WORKAROUND_CVE_2018_3639
|
||||
/*
|
||||
* This macro applies the mitigation for CVE-2018-3639.
|
||||
|
|
@ -428,7 +430,7 @@ check_erratum_custom_end cortex_a76, ERRATUM(1165522)
|
|||
check_erratum_chosen cortex_a76, CVE(2022, 23960), WORKAROUND_CVE_2022_23960
|
||||
|
||||
/* erratum has no workaround in the cpu. Generic code must take care */
|
||||
add_erratum_entry cortex_a76, CVE(2022, 23960), WORKAROUND_CVE_2022_23960, NO_APPLY_AT_RESET
|
||||
add_erratum_entry cortex_a76, CVE(2022, 23960), WORKAROUND_CVE_2022_23960
|
||||
|
||||
workaround_reset_start cortex_a76, ERRATUM(798953), ERRATA_DSU_798953
|
||||
errata_dsu_798953_wa_impl
|
||||
|
|
|
|||
|
|
@ -1,5 +1,5 @@
|
|||
/*
|
||||
* Copyright (c) 2019-2024, Arm Limited. All rights reserved.
|
||||
* Copyright (c) 2019-2025, Arm Limited. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
|
@ -21,6 +21,8 @@
|
|||
#error "Cortex-A76AE supports only AArch64. Compile with CTX_INCLUDE_AARCH32_REGS=0"
|
||||
#endif
|
||||
|
||||
cpu_reset_prologue cortex_a76ae
|
||||
|
||||
#if WORKAROUND_CVE_2022_23960
|
||||
wa_cve_2022_23960_bhb_vector_table CORTEX_A76AE_BHB_LOOP_COUNT, cortex_a76ae
|
||||
#endif /* WORKAROUND_CVE_2022_23960 */
|
||||
|
|
|
|||
|
|
@ -17,6 +17,8 @@
|
|||
#error "Cortex-A77 must be compiled with HW_ASSISTED_COHERENCY enabled"
|
||||
#endif
|
||||
|
||||
cpu_reset_prologue cortex_a77
|
||||
|
||||
/* 64-bit only core */
|
||||
#if CTX_INCLUDE_AARCH32_REGS == 1
|
||||
#error "Cortex-A77 supports only AArch64. Compile with CTX_INCLUDE_AARCH32_REGS=0"
|
||||
|
|
|
|||
|
|
@ -1,5 +1,5 @@
|
|||
/*
|
||||
* Copyright (c) 2019-2024, Arm Limited. All rights reserved.
|
||||
* Copyright (c) 2019-2025, Arm Limited. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
|
@ -24,6 +24,8 @@
|
|||
wa_cve_2022_23960_bhb_vector_table CORTEX_A78_BHB_LOOP_COUNT, cortex_a78
|
||||
#endif /* WORKAROUND_CVE_2022_23960 */
|
||||
|
||||
cpu_reset_prologue cortex_a78
|
||||
|
||||
/* Disable hardware page aggregation.Enables mitigation for `CVE-2024-5660` */
|
||||
workaround_reset_start cortex_a78, CVE(2024, 5660), WORKAROUND_CVE_2024_5660
|
||||
sysreg_bit_set CORTEX_A78_CPUECTLR_EL1, BIT(46)
|
||||
|
|
|
|||
|
|
@ -1,5 +1,5 @@
|
|||
/*
|
||||
* Copyright (c) 2019-2024, Arm Limited. All rights reserved.
|
||||
* Copyright (c) 2019-2025, Arm Limited. All rights reserved.
|
||||
* Copyright (c) 2021-2023, NVIDIA Corporation. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
|
|
@ -22,6 +22,8 @@
|
|||
wa_cve_2022_23960_bhb_vector_table CORTEX_A78_AE_BHB_LOOP_COUNT, cortex_a78_ae
|
||||
#endif /* WORKAROUND_CVE_2022_23960 */
|
||||
|
||||
cpu_reset_prologue cortex_a78_ae
|
||||
|
||||
/* Disable hardware page aggregation. Enables mitigation for `CVE-2024-5660` */
|
||||
workaround_reset_start cortex_a78_ae, CVE(2024, 5660), WORKAROUND_CVE_2024_5660
|
||||
sysreg_bit_set CORTEX_A78_AE_CPUECTLR_EL1, BIT(46)
|
||||
|
|
|
|||
|
|
@ -1,5 +1,5 @@
|
|||
/*
|
||||
* Copyright (c) 2021-2024, Arm Limited. All rights reserved.
|
||||
* Copyright (c) 2021-2025, Arm Limited. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
|
@ -21,6 +21,8 @@
|
|||
wa_cve_2022_23960_bhb_vector_table CORTEX_A78C_BHB_LOOP_COUNT, cortex_a78c
|
||||
#endif /* WORKAROUND_CVE_2022_23960 */
|
||||
|
||||
cpu_reset_prologue cortex_a78c
|
||||
|
||||
/* Disable hardware page aggregation. Enables mitigation for `CVE-2024-5660` */
|
||||
workaround_reset_start cortex_a78c, CVE(2024, 5660), WORKAROUND_CVE_2024_5660
|
||||
sysreg_bit_set CORTEX_A78C_CPUECTLR_EL1, BIT(46)
|
||||
|
|
|
|||
|
|
@ -1,5 +1,5 @@
|
|||
/*
|
||||
* Copyright (c) 2024, Arm Limited. All rights reserved.
|
||||
* Copyright (c) 2024-2025, Arm Limited. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
|
@ -25,6 +25,8 @@
|
|||
#error "Travis needs ERRATA_SME_POWER_DOWN=1 to powerdown correctly"
|
||||
#endif
|
||||
|
||||
cpu_reset_prologue cortex_alto
|
||||
|
||||
cpu_reset_func_start cortex_alto
|
||||
/* Disable speculative loads */
|
||||
msr SSBS, xzr
|
||||
|
|
|
|||
|
|
@ -1,5 +1,5 @@
|
|||
/*
|
||||
* Copyright (c) 2024, Arm Limited. All rights reserved.
|
||||
* Copyright (c) 2024-2025, Arm Limited. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
|
@ -21,6 +21,8 @@
|
|||
#error "Cortex-ARCADIA supports only AArch64. Compile with CTX_INCLUDE_AARCH32_REGS=0"
|
||||
#endif
|
||||
|
||||
cpu_reset_prologue cortex_arcadia
|
||||
|
||||
cpu_reset_func_start cortex_arcadia
|
||||
/* Disable speculative loads */
|
||||
msr SSBS, xzr
|
||||
|
|
|
|||
|
|
@ -29,6 +29,8 @@
|
|||
#error "Gelas needs ERRATA_SME_POWER_DOWN=1 to powerdown correctly"
|
||||
#endif
|
||||
|
||||
cpu_reset_prologue cortex_gelas
|
||||
|
||||
cpu_reset_func_start cortex_gelas
|
||||
/* ----------------------------------------------------
|
||||
* Disable speculative loads
|
||||
|
|
|
|||
|
|
@ -23,6 +23,8 @@
|
|||
wa_cve_2022_23960_bhb_vector_table CORTEX_X1_BHB_LOOP_COUNT, cortex_x1
|
||||
#endif /* WORKAROUND_CVE_2022_23960 */
|
||||
|
||||
cpu_reset_prologue cortex_x1
|
||||
|
||||
/* Disable hardware page aggregation. Enables mitigation for `CVE-2024-5660` */
|
||||
workaround_reset_start cortex_x1, CVE(2024, 5660), WORKAROUND_CVE_2024_5660
|
||||
sysreg_bit_set CORTEX_X1_CPUECTLR_EL1, BIT(46)
|
||||
|
|
|
|||
|
|
@ -25,7 +25,7 @@
|
|||
|
||||
.global check_erratum_cortex_x2_3701772
|
||||
|
||||
add_erratum_entry cortex_x2, ERRATUM(3701772), ERRATA_X2_3701772, NO_APPLY_AT_RESET
|
||||
add_erratum_entry cortex_x2, ERRATUM(3701772), ERRATA_X2_3701772
|
||||
|
||||
check_erratum_ls cortex_x2, ERRATUM(3701772), CPU_REV(2, 1)
|
||||
|
||||
|
|
@ -33,6 +33,8 @@ check_erratum_ls cortex_x2, ERRATUM(3701772), CPU_REV(2, 1)
|
|||
wa_cve_2022_23960_bhb_vector_table CORTEX_X2_BHB_LOOP_COUNT, cortex_x2
|
||||
#endif /* WORKAROUND_CVE_2022_23960 */
|
||||
|
||||
cpu_reset_prologue cortex_x2
|
||||
|
||||
/* Disable hardware page aggregation. Enables mitigation for `CVE-2024-5660` */
|
||||
workaround_reset_start cortex_x2, CVE(2024, 5660), WORKAROUND_CVE_2024_5660
|
||||
sysreg_bit_set CORTEX_X2_CPUECTLR_EL1, BIT(46)
|
||||
|
|
|
|||
|
|
@ -24,7 +24,7 @@
|
|||
|
||||
.global check_erratum_cortex_x3_3701769
|
||||
|
||||
add_erratum_entry cortex_x3, ERRATUM(3701769), ERRATA_X3_3701769, NO_APPLY_AT_RESET
|
||||
add_erratum_entry cortex_x3, ERRATUM(3701769), ERRATA_X3_3701769
|
||||
|
||||
check_erratum_ls cortex_x3, ERRATUM(3701769), CPU_REV(1, 2)
|
||||
|
||||
|
|
@ -32,6 +32,8 @@ check_erratum_ls cortex_x3, ERRATUM(3701769), CPU_REV(1, 2)
|
|||
wa_cve_2022_23960_bhb_vector_table CORTEX_X3_BHB_LOOP_COUNT, cortex_x3
|
||||
#endif /* WORKAROUND_CVE_2022_23960 */
|
||||
|
||||
cpu_reset_prologue cortex_x3
|
||||
|
||||
/* Disable hardware page aggregation. Enables mitigation for `CVE-2024-5660` */
|
||||
workaround_reset_start cortex_x3, CVE(2024, 5660), WORKAROUND_CVE_2024_5660
|
||||
sysreg_bit_set CORTEX_X3_CPUECTLR_EL1, BIT(46)
|
||||
|
|
|
|||
|
|
@ -22,6 +22,8 @@
|
|||
#error "Cortex X4 supports only AArch64. Compile with CTX_INCLUDE_AARCH32_REGS=0"
|
||||
#endif
|
||||
|
||||
cpu_reset_prologue cortex_x4
|
||||
|
||||
.global check_erratum_cortex_x4_2726228
|
||||
.global check_erratum_cortex_x4_3701758
|
||||
|
||||
|
|
@ -122,7 +124,7 @@ workaround_reset_end cortex_x4, CVE(2024, 7881)
|
|||
|
||||
check_erratum_chosen cortex_x4, CVE(2024, 7881), WORKAROUND_CVE_2024_7881
|
||||
|
||||
add_erratum_entry cortex_x4, ERRATUM(3701758), ERRATA_X4_3701758, NO_APPLY_AT_RESET
|
||||
add_erratum_entry cortex_x4, ERRATUM(3701758), ERRATA_X4_3701758
|
||||
|
||||
check_erratum_ls cortex_x4, ERRATUM(3701758), CPU_REV(0, 3)
|
||||
|
||||
|
|
|
|||
|
|
@ -21,9 +21,9 @@
|
|||
#error "Cortex-X925 supports only AArch64. Compile with CTX_INCLUDE_AARCH32_REGS=0"
|
||||
#endif
|
||||
|
||||
.global check_erratum_cortex_x925_3701747
|
||||
cpu_reset_prologue cortex_x925
|
||||
|
||||
add_erratum_entry cortex_x925, ERRATUM(3701747), ERRATA_X925_3701747, NO_APPLY_AT_RESET
|
||||
add_erratum_entry cortex_x925, ERRATUM(3701747), ERRATA_X925_3701747
|
||||
|
||||
check_erratum_ls cortex_x925, ERRATUM(3701747), CPU_REV(0, 1)
|
||||
|
||||
|
|
|
|||
|
|
@ -1,5 +1,5 @@
|
|||
/*
|
||||
* Copyright (c) 2015-2024, Arm Limited and Contributors. All rights reserved.
|
||||
* Copyright (c) 2015-2025, Arm Limited and Contributors. All rights reserved.
|
||||
* Copyright (c) 2020-2022, NVIDIA Corporation. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
|
|
@ -13,6 +13,8 @@
|
|||
#include <cpu_macros.S>
|
||||
#include <plat_macros.S>
|
||||
|
||||
cpu_reset_prologue denver
|
||||
|
||||
/* -------------------------------------------------
|
||||
* CVE-2017-5715 mitigation
|
||||
*
|
||||
|
|
|
|||
|
|
@ -1,5 +1,5 @@
|
|||
/*
|
||||
* Copyright (c) 2020-2024, Arm Limited. All rights reserved.
|
||||
* Copyright (c) 2020-2025, Arm Limited. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
|
@ -11,6 +11,8 @@
|
|||
#include <cpu_macros.S>
|
||||
#include <plat_macros.S>
|
||||
|
||||
cpu_reset_prologue generic
|
||||
|
||||
/* ---------------------------------------------
|
||||
* Disable L1 data cache and unified L2 cache
|
||||
* ---------------------------------------------
|
||||
|
|
|
|||
|
|
@ -22,6 +22,8 @@
|
|||
#error "Neoverse-E1 supports only AArch64. Compile with CTX_INCLUDE_AARCH32_REGS=0"
|
||||
#endif
|
||||
|
||||
cpu_reset_prologue neoverse_e1
|
||||
|
||||
workaround_reset_start neoverse_e1, ERRATUM(936184), ERRATA_DSU_936184
|
||||
errata_dsu_936184_wa_impl
|
||||
workaround_reset_end neoverse_e1, ERRATUM(936184)
|
||||
|
|
|
|||
|
|
@ -28,6 +28,8 @@
|
|||
wa_cve_2022_23960_bhb_vector_table NEOVERSE_N1_BHB_LOOP_COUNT, neoverse_n1
|
||||
#endif /* WORKAROUND_CVE_2022_23960 */
|
||||
|
||||
cpu_reset_prologue neoverse_n1
|
||||
|
||||
workaround_reset_start neoverse_n1, ERRATUM(936184), ERRATA_DSU_936184
|
||||
errata_dsu_936184_wa_impl
|
||||
workaround_reset_end neoverse_n1, ERRATUM(936184)
|
||||
|
|
|
|||
|
|
@ -23,7 +23,7 @@
|
|||
|
||||
.global check_erratum_neoverse_n2_3701773
|
||||
|
||||
add_erratum_entry neoverse_n2, ERRATUM(3701773), ERRATA_N2_3701773, NO_APPLY_AT_RESET
|
||||
add_erratum_entry neoverse_n2, ERRATUM(3701773), ERRATA_N2_3701773
|
||||
|
||||
check_erratum_ls neoverse_n2, ERRATUM(3701773), CPU_REV(0, 3)
|
||||
|
||||
|
|
@ -31,6 +31,8 @@ check_erratum_ls neoverse_n2, ERRATUM(3701773), CPU_REV(0, 3)
|
|||
wa_cve_2022_23960_bhb_vector_table NEOVERSE_N2_BHB_LOOP_COUNT, neoverse_n2
|
||||
#endif /* WORKAROUND_CVE_2022_23960 */
|
||||
|
||||
cpu_reset_prologue neoverse_n2
|
||||
|
||||
workaround_reset_start neoverse_n2, ERRATUM(2313941), ERRATA_DSU_2313941
|
||||
errata_dsu_2313941_wa_impl
|
||||
workaround_reset_end neoverse_n2, ERRATUM(2313941)
|
||||
|
|
|
|||
|
|
@ -21,9 +21,11 @@
|
|||
#error "Neoverse-N3 supports only AArch64. Compile with CTX_INCLUDE_AARCH32_REGS=0"
|
||||
#endif
|
||||
|
||||
cpu_reset_prologue neoverse_n3
|
||||
|
||||
.global check_erratum_neoverse_n3_3699563
|
||||
|
||||
add_erratum_entry neoverse_n3, ERRATUM(3699563), ERRATA_N3_3699563, NO_APPLY_AT_RESET
|
||||
add_erratum_entry neoverse_n3, ERRATUM(3699563), ERRATA_N3_3699563
|
||||
|
||||
check_erratum_ls neoverse_n3, ERRATUM(3699563), CPU_REV(0, 0)
|
||||
|
||||
|
|
|
|||
|
|
@ -22,6 +22,8 @@
|
|||
#error "Neoverse-V1 supports only AArch64. Compile with CTX_INCLUDE_AARCH32_REGS=0"
|
||||
#endif
|
||||
|
||||
cpu_reset_prologue neoverse_v1
|
||||
|
||||
#if WORKAROUND_CVE_2022_23960
|
||||
wa_cve_2022_23960_bhb_vector_table NEOVERSE_V1_BHB_LOOP_COUNT, neoverse_v1
|
||||
#endif /* WORKAROUND_CVE_2022_23960 */
|
||||
|
|
|
|||
|
|
@ -22,6 +22,8 @@
|
|||
#error "Neoverse V2 supports only AArch64. Compile with CTX_INCLUDE_AARCH32_REGS=0"
|
||||
#endif
|
||||
|
||||
cpu_reset_prologue neoverse_v2
|
||||
|
||||
/* Disable hardware page aggregation. Enables mitigation for `CVE-2024-5660` */
|
||||
workaround_reset_start neoverse_v2, CVE(2024, 5660), WORKAROUND_CVE_2024_5660
|
||||
sysreg_bit_set NEOVERSE_V2_CPUECTLR_EL1, BIT(46)
|
||||
|
|
|
|||
|
|
@ -22,9 +22,11 @@
|
|||
#error "Neoverse V3 supports only AArch64. Compile with CTX_INCLUDE_AARCH32_REGS=0"
|
||||
#endif
|
||||
|
||||
cpu_reset_prologue neoverse_v3
|
||||
|
||||
.global check_erratum_neoverse_v3_3701767
|
||||
|
||||
add_erratum_entry neoverse_v3, ERRATUM(3701767), ERRATA_V3_3701767, NO_APPLY_AT_RESET
|
||||
add_erratum_entry neoverse_v3, ERRATUM(3701767), ERRATA_V3_3701767
|
||||
|
||||
check_erratum_ls neoverse_v3, ERRATUM(3701767), CPU_REV(0, 2)
|
||||
|
||||
|
|
|
|||
|
|
@ -1,5 +1,5 @@
|
|||
/*
|
||||
* Copyright (c) 2023-2024, Arm Limited. All rights reserved.
|
||||
* Copyright (c) 2023-2025, Arm Limited. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
|
@ -21,6 +21,8 @@
|
|||
#error "Nevis supports only AArch64. Compile with CTX_INCLUDE_AARCH32_REGS=0"
|
||||
#endif
|
||||
|
||||
cpu_reset_prologue nevis
|
||||
|
||||
cpu_reset_func_start nevis
|
||||
/* ----------------------------------------------------
|
||||
* Disable speculative loads
|
||||
|
|
|
|||
|
|
@ -8,6 +8,8 @@
|
|||
#include <cpu_macros.S>
|
||||
#include <qemu_max.h>
|
||||
|
||||
cpu_reset_prologue qemu_max
|
||||
|
||||
func qemu_max_core_pwr_dwn
|
||||
/* ---------------------------------------------
|
||||
* Disable the Data Cache.
|
||||
|
|
|
|||
|
|
@ -1,5 +1,5 @@
|
|||
/*
|
||||
* Copyright (c) 2020-2024, Arm Limited. All rights reserved.
|
||||
* Copyright (c) 2020-2025, Arm Limited. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
|
@ -21,6 +21,8 @@
|
|||
#error "Rainier CPU supports only AArch64. Compile with CTX_INCLUDE_AARCH32_REGS=0"
|
||||
#endif
|
||||
|
||||
cpu_reset_prologue rainier
|
||||
|
||||
/* --------------------------------------------------
|
||||
* Disable speculative loads if Rainier supports
|
||||
* SSBS.
|
||||
|
|
|
|||
|
|
@ -29,6 +29,8 @@
|
|||
#error "Travis needs ERRATA_SME_POWER_DOWN=1 to powerdown correctly"
|
||||
#endif
|
||||
|
||||
cpu_reset_prologue travis
|
||||
|
||||
cpu_reset_func_start travis
|
||||
/* ----------------------------------------------------
|
||||
* Disable speculative loads
|
||||
|
|
|
|||
Loading…
Add table
Reference in a new issue