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89dba82dfa
Errata application is painful for performance. For a start, it's done when the core has just come out of reset, which means branch predictors and caches will be empty so a branch to a workaround function must be fetched from memory and that round trip is very slow. Then it also runs with the I-cache off, which means that the loop to iterate over the workarounds must also be fetched from memory on each iteration. We can remove both branches. First, we can simply apply every erratum directly instead of defining a workaround function and jumping to it. Currently, no errata that need to be applied at both reset and runtime, with the same workaround function, exist. If the need arose in future, this should be achievable with a reset + runtime wrapper combo. Then, we can construct a function that applies each erratum linearly instead of looping over the list. If this function is part of the reset function, then the only "far" branches at reset will be for the checker functions. Importantly, this mitigates the slowdown even when an erratum is disabled. The result is ~50% speedup on N1SDP and ~20% on AArch64 Juno on wakeup from PSCI calls that end in powerdown. This is roughly back to the baseline of v2.9, before the errata framework regressed on performance (or a little better). It is important to note that there are other slowdowns since then that remain unknown. Change-Id: Ie4d5288a331b11fd648e5c4a0b652b74160b07b9 Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>
305 lines
9.6 KiB
ArmAsm
305 lines
9.6 KiB
ArmAsm
/*
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* Copyright (c) 2017-2025, Arm Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <arch.h>
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#include <asm_macros.S>
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#include <cpuamu.h>
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#include <cpu_macros.S>
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#include <dsu_macros.S>
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#include <neoverse_n1.h>
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#include "wa_cve_2022_23960_bhb_vector.S"
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/* Hardware handled coherency */
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#if HW_ASSISTED_COHERENCY == 0
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#error "Neoverse N1 must be compiled with HW_ASSISTED_COHERENCY enabled"
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#endif
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/* 64-bit only core */
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#if CTX_INCLUDE_AARCH32_REGS == 1
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#error "Neoverse-N1 supports only AArch64. Compile with CTX_INCLUDE_AARCH32_REGS=0"
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#endif
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.global neoverse_n1_errata_ic_trap_handler
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#if WORKAROUND_CVE_2022_23960
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wa_cve_2022_23960_bhb_vector_table NEOVERSE_N1_BHB_LOOP_COUNT, neoverse_n1
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#endif /* WORKAROUND_CVE_2022_23960 */
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cpu_reset_prologue neoverse_n1
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workaround_reset_start neoverse_n1, ERRATUM(936184), ERRATA_DSU_936184
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errata_dsu_936184_wa_impl
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workaround_reset_end neoverse_n1, ERRATUM(936184)
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check_erratum_custom_start neoverse_n1, ERRATUM(936184)
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branch_if_scu_not_present 2f /* label 1 is used in the macro */
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check_errata_dsu_936184_impl
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2:
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ret
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check_erratum_custom_end neoverse_n1, ERRATUM(936184)
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workaround_reset_start neoverse_n1, ERRATUM(1043202), ERRATA_N1_1043202
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/* Apply instruction patching sequence */
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ldr x0, =0x0
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msr CPUPSELR_EL3, x0
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ldr x0, =0xF3BF8F2F
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msr CPUPOR_EL3, x0
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ldr x0, =0xFFFFFFFF
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msr CPUPMR_EL3, x0
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ldr x0, =0x800200071
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msr CPUPCR_EL3, x0
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workaround_reset_end neoverse_n1, ERRATUM(1043202)
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check_erratum_ls neoverse_n1, ERRATUM(1043202), CPU_REV(1, 0)
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workaround_reset_start neoverse_n1, ERRATUM(1073348), ERRATA_N1_1073348
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sysreg_bit_set NEOVERSE_N1_CPUACTLR_EL1, NEOVERSE_N1_CPUACTLR_EL1_BIT_6
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workaround_reset_end neoverse_n1, ERRATUM(1073348)
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check_erratum_ls neoverse_n1, ERRATUM(1073348), CPU_REV(1, 0)
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workaround_reset_start neoverse_n1, ERRATUM(1130799), ERRATA_N1_1130799
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sysreg_bit_set NEOVERSE_N1_CPUACTLR2_EL1, NEOVERSE_N1_CPUACTLR2_EL1_BIT_59
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workaround_reset_end neoverse_n1, ERRATUM(1130799)
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check_erratum_ls neoverse_n1, ERRATUM(1130799), CPU_REV(2, 0)
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workaround_reset_start neoverse_n1, ERRATUM(1165347), ERRATA_N1_1165347
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sysreg_bit_set NEOVERSE_N1_CPUACTLR2_EL1, NEOVERSE_N1_CPUACTLR2_EL1_BIT_0
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sysreg_bit_set NEOVERSE_N1_CPUACTLR2_EL1, NEOVERSE_N1_CPUACTLR2_EL1_BIT_15
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workaround_reset_end neoverse_n1, ERRATUM(1165347)
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check_erratum_ls neoverse_n1, ERRATUM(1165347), CPU_REV(2, 0)
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workaround_reset_start neoverse_n1, ERRATUM(1207823), ERRATA_N1_1207823
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sysreg_bit_set NEOVERSE_N1_CPUACTLR2_EL1, NEOVERSE_N1_CPUACTLR2_EL1_BIT_11
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workaround_reset_end neoverse_n1, ERRATUM(1207823)
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check_erratum_ls neoverse_n1, ERRATUM(1207823), CPU_REV(2, 0)
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workaround_reset_start neoverse_n1, ERRATUM(1220197), ERRATA_N1_1220197
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sysreg_bit_set NEOVERSE_N1_CPUECTLR_EL1, NEOVERSE_N1_WS_THR_L2_MASK
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workaround_reset_end neoverse_n1, ERRATUM(1220197)
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check_erratum_ls neoverse_n1, ERRATUM(1220197), CPU_REV(2, 0)
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workaround_reset_start neoverse_n1, ERRATUM(1257314), ERRATA_N1_1257314
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sysreg_bit_set NEOVERSE_N1_CPUACTLR3_EL1, NEOVERSE_N1_CPUACTLR3_EL1_BIT_10
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workaround_reset_end neoverse_n1, ERRATUM(1257314)
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check_erratum_ls neoverse_n1, ERRATUM(1257314), CPU_REV(3, 0)
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workaround_reset_start neoverse_n1, ERRATUM(1262606), ERRATA_N1_1262606
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sysreg_bit_set NEOVERSE_N1_CPUACTLR_EL1, NEOVERSE_N1_CPUACTLR_EL1_BIT_13
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workaround_reset_end neoverse_n1, ERRATUM(1262606)
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check_erratum_ls neoverse_n1, ERRATUM(1262606), CPU_REV(3, 0)
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workaround_reset_start neoverse_n1, ERRATUM(1262888), ERRATA_N1_1262888
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sysreg_bit_set NEOVERSE_N1_CPUECTLR_EL1, NEOVERSE_N1_CPUECTLR_EL1_MM_TLBPF_DIS_BIT
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workaround_reset_end neoverse_n1, ERRATUM(1262888)
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check_erratum_ls neoverse_n1, ERRATUM(1262888), CPU_REV(3, 0)
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workaround_reset_start neoverse_n1, ERRATUM(1275112), ERRATA_N1_1275112
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sysreg_bit_set NEOVERSE_N1_CPUACTLR_EL1, NEOVERSE_N1_CPUACTLR_EL1_BIT_13
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workaround_reset_end neoverse_n1, ERRATUM(1275112)
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check_erratum_ls neoverse_n1, ERRATUM(1275112), CPU_REV(3, 0)
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workaround_reset_start neoverse_n1, ERRATUM(1315703), ERRATA_N1_1315703
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sysreg_bit_set NEOVERSE_N1_CPUACTLR2_EL1, NEOVERSE_N1_CPUACTLR2_EL1_BIT_16
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workaround_reset_end neoverse_n1, ERRATUM(1315703)
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check_erratum_ls neoverse_n1, ERRATUM(1315703), CPU_REV(3, 0)
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workaround_reset_start neoverse_n1, ERRATUM(1542419), ERRATA_N1_1542419
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/* Apply instruction patching sequence */
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ldr x0, =0x0
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msr CPUPSELR_EL3, x0
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ldr x0, =0xEE670D35
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msr CPUPOR_EL3, x0
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ldr x0, =0xFFFF0FFF
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msr CPUPMR_EL3, x0
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ldr x0, =0x08000020007D
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msr CPUPCR_EL3, x0
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isb
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workaround_reset_end neoverse_n1, ERRATUM(1542419)
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check_erratum_range neoverse_n1, ERRATUM(1542419), CPU_REV(3, 0), CPU_REV(4, 0)
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workaround_reset_start neoverse_n1, ERRATUM(1868343), ERRATA_N1_1868343
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sysreg_bit_set NEOVERSE_N1_CPUACTLR_EL1, NEOVERSE_N1_CPUACTLR_EL1_BIT_13
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workaround_reset_end neoverse_n1, ERRATUM(1868343)
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check_erratum_ls neoverse_n1, ERRATUM(1868343), CPU_REV(4, 0)
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workaround_reset_start neoverse_n1, ERRATUM(1946160), ERRATA_N1_1946160
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mov x0, #3
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msr S3_6_C15_C8_0, x0
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ldr x0, =0x10E3900002
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msr S3_6_C15_C8_2, x0
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ldr x0, =0x10FFF00083
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msr S3_6_C15_C8_3, x0
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ldr x0, =0x2001003FF
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msr S3_6_C15_C8_1, x0
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mov x0, #4
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msr S3_6_C15_C8_0, x0
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ldr x0, =0x10E3800082
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msr S3_6_C15_C8_2, x0
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ldr x0, =0x10FFF00083
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msr S3_6_C15_C8_3, x0
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ldr x0, =0x2001003FF
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msr S3_6_C15_C8_1, x0
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mov x0, #5
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msr S3_6_C15_C8_0, x0
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ldr x0, =0x10E3800200
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msr S3_6_C15_C8_2, x0
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ldr x0, =0x10FFF003E0
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msr S3_6_C15_C8_3, x0
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ldr x0, =0x2001003FF
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msr S3_6_C15_C8_1, x0
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isb
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workaround_reset_end neoverse_n1, ERRATUM(1946160)
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check_erratum_range neoverse_n1, ERRATUM(1946160), CPU_REV(3, 0), CPU_REV(4, 1)
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workaround_runtime_start neoverse_n1, ERRATUM(2743102), ERRATA_N1_2743102
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/* dsb before isb of power down sequence */
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dsb sy
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workaround_runtime_end neoverse_n1, ERRATUM(2743102)
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check_erratum_ls neoverse_n1, ERRATUM(2743102), CPU_REV(4, 1)
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workaround_reset_start neoverse_n1, CVE(2022, 23960), WORKAROUND_CVE_2022_23960
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#if IMAGE_BL31
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/*
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* The Neoverse-N1 generic vectors are overridden to apply errata
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* mitigation on exception entry from lower ELs.
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*/
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override_vector_table wa_cve_vbar_neoverse_n1
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#endif /* IMAGE_BL31 */
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workaround_reset_end neoverse_n1, CVE(2022, 23960)
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check_erratum_chosen neoverse_n1, CVE(2022, 23960), WORKAROUND_CVE_2022_23960
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/* --------------------------------------------------
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* Disable speculative loads if Neoverse N1 supports
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* SSBS.
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*
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* Shall clobber: x0.
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* --------------------------------------------------
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*/
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func neoverse_n1_disable_speculative_loads
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/* Check if the PE implements SSBS */
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mrs x0, id_aa64pfr1_el1
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tst x0, #(ID_AA64PFR1_EL1_SSBS_MASK << ID_AA64PFR1_EL1_SSBS_SHIFT)
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b.eq 1f
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/* Disable speculative loads */
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msr SSBS, xzr
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1:
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ret
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endfunc neoverse_n1_disable_speculative_loads
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cpu_reset_func_start neoverse_n1
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bl neoverse_n1_disable_speculative_loads
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/* Forces all cacheable atomic instructions to be near */
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sysreg_bit_set NEOVERSE_N1_CPUACTLR2_EL1, NEOVERSE_N1_CPUACTLR2_EL1_BIT_2
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isb
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#if ENABLE_FEAT_AMU
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/* Make sure accesses from EL0/EL1 and EL2 are not trapped to EL3 */
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sysreg_bit_set actlr_el3, NEOVERSE_N1_ACTLR_AMEN_BIT
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/* Make sure accesses from EL0/EL1 are not trapped to EL2 */
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sysreg_bit_set actlr_el2, NEOVERSE_N1_ACTLR_AMEN_BIT
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/* Enable group0 counters */
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mov x0, #NEOVERSE_N1_AMU_GROUP0_MASK
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msr CPUAMCNTENSET_EL0, x0
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#endif
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#if NEOVERSE_Nx_EXTERNAL_LLC
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/* Some system may have External LLC, core needs to be made aware */
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sysreg_bit_set NEOVERSE_N1_CPUECTLR_EL1, NEOVERSE_N1_CPUECTLR_EL1_EXTLLC_BIT
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#endif
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cpu_reset_func_end neoverse_n1
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/* ---------------------------------------------
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* HW will do the cache maintenance while powering down
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* ---------------------------------------------
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*/
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func neoverse_n1_core_pwr_dwn
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/* ---------------------------------------------
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* Enable CPU power down bit in power control register
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* ---------------------------------------------
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*/
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sysreg_bit_set NEOVERSE_N1_CPUPWRCTLR_EL1, NEOVERSE_N1_CORE_PWRDN_EN_MASK
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apply_erratum neoverse_n1, ERRATUM(2743102), ERRATA_N1_2743102, NO_GET_CPU_REV
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isb
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ret
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endfunc neoverse_n1_core_pwr_dwn
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/*
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* Handle trap of EL0 IC IVAU instructions to EL3 by executing a TLB
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* inner-shareable invalidation to an arbitrary address followed by a DSB.
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*
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* x1: Exception Syndrome
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*/
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func neoverse_n1_errata_ic_trap_handler
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cmp x1, #NEOVERSE_N1_EC_IC_TRAP
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b.ne 1f
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tlbi vae3is, xzr
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dsb sy
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# Skip the IC instruction itself
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mrs x3, elr_el3
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add x3, x3, #4
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msr elr_el3, x3
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ldp x0, x1, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X0]
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ldp x2, x3, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X2]
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ldp x4, x5, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X4]
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ldr x30, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_LR]
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/*
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* Issue Error Synchronization Barrier to synchronize SErrors before
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* exiting EL3. We're running with EAs unmasked, so any synchronized
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* errors would be taken immediately; therefore no need to inspect
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* DISR_EL1 register.
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*/
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esb
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exception_return
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1:
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ret
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endfunc neoverse_n1_errata_ic_trap_handler
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/* ---------------------------------------------
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* This function provides neoverse_n1 specific
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* register information for crash reporting.
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* It needs to return with x6 pointing to
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* a list of register names in ascii and
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* x8 - x15 having values of registers to be
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* reported.
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* ---------------------------------------------
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*/
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.section .rodata.neoverse_n1_regs, "aS"
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neoverse_n1_regs: /* The ascii list of register names to be reported */
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.asciz "cpuectlr_el1", ""
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func neoverse_n1_cpu_reg_dump
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adr x6, neoverse_n1_regs
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mrs x8, NEOVERSE_N1_CPUECTLR_EL1
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ret
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endfunc neoverse_n1_cpu_reg_dump
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declare_cpu_ops_eh neoverse_n1, NEOVERSE_N1_MIDR, \
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neoverse_n1_reset_func, \
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neoverse_n1_errata_ic_trap_handler, \
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neoverse_n1_core_pwr_dwn
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