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89dba82dfa
Errata application is painful for performance. For a start, it's done when the core has just come out of reset, which means branch predictors and caches will be empty so a branch to a workaround function must be fetched from memory and that round trip is very slow. Then it also runs with the I-cache off, which means that the loop to iterate over the workarounds must also be fetched from memory on each iteration. We can remove both branches. First, we can simply apply every erratum directly instead of defining a workaround function and jumping to it. Currently, no errata that need to be applied at both reset and runtime, with the same workaround function, exist. If the need arose in future, this should be achievable with a reset + runtime wrapper combo. Then, we can construct a function that applies each erratum linearly instead of looping over the list. If this function is part of the reset function, then the only "far" branches at reset will be for the checker functions. Importantly, this mitigates the slowdown even when an erratum is disabled. The result is ~50% speedup on N1SDP and ~20% on AArch64 Juno on wakeup from PSCI calls that end in powerdown. This is roughly back to the baseline of v2.9, before the errata framework regressed on performance (or a little better). It is important to note that there are other slowdowns since then that remain unknown. Change-Id: Ie4d5288a331b11fd648e5c4a0b652b74160b07b9 Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>
303 lines
8.5 KiB
ArmAsm
303 lines
8.5 KiB
ArmAsm
/*
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* Copyright (c) 2015-2025, Arm Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <arch.h>
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#include <asm_macros.S>
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#include <assert_macros.S>
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#include <cortex_a72.h>
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#include <cpu_macros.S>
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#include <plat_macros.S>
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#include "wa_cve_2022_23960_bhb_vector.S"
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#if WORKAROUND_CVE_2022_23960
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wa_cve_2022_23960_bhb_vector_table CORTEX_A72_BHB_LOOP_COUNT, cortex_a72
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#endif /* WORKAROUND_CVE_2022_23960 */
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cpu_reset_prologue cortex_a72
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/* ---------------------------------------------
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* Disable L1 data cache and unified L2 cache
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* ---------------------------------------------
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*/
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func cortex_a72_disable_dcache
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mrs x1, sctlr_el3
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bic x1, x1, #SCTLR_C_BIT
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msr sctlr_el3, x1
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isb
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ret
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endfunc cortex_a72_disable_dcache
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/* ---------------------------------------------
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* Disable all types of L2 prefetches.
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* ---------------------------------------------
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*/
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func cortex_a72_disable_l2_prefetch
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mrs x0, CORTEX_A72_ECTLR_EL1
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orr x0, x0, #CORTEX_A72_ECTLR_DIS_TWD_ACC_PFTCH_BIT
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mov x1, #CORTEX_A72_ECTLR_L2_IPFTCH_DIST_MASK
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orr x1, x1, #CORTEX_A72_ECTLR_L2_DPFTCH_DIST_MASK
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bic x0, x0, x1
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msr CORTEX_A72_ECTLR_EL1, x0
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isb
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ret
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endfunc cortex_a72_disable_l2_prefetch
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/* ---------------------------------------------
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* Disable the load-store hardware prefetcher.
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* ---------------------------------------------
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*/
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func cortex_a72_disable_hw_prefetcher
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sysreg_bit_set CORTEX_A72_CPUACTLR_EL1, CORTEX_A72_CPUACTLR_EL1_DISABLE_L1_DCACHE_HW_PFTCH
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isb
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dsb ish
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ret
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endfunc cortex_a72_disable_hw_prefetcher
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/* ---------------------------------------------
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* Disable intra-cluster coherency
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* ---------------------------------------------
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*/
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func cortex_a72_disable_smp
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sysreg_bit_clear CORTEX_A72_ECTLR_EL1, CORTEX_A72_ECTLR_SMP_BIT
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ret
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endfunc cortex_a72_disable_smp
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/* ---------------------------------------------
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* Disable debug interfaces
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* ---------------------------------------------
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*/
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func cortex_a72_disable_ext_debug
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mov x0, #1
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msr osdlr_el1, x0
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isb
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dsb sy
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ret
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endfunc cortex_a72_disable_ext_debug
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func check_smccc_arch_workaround_3
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cpu_check_csv2 x0, 1f
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mov x0, #ERRATA_APPLIES
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ret
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1:
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mov x0, #ERRATA_NOT_APPLIES
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ret
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endfunc check_smccc_arch_workaround_3
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workaround_reset_start cortex_a72, ERRATUM(859971), ERRATA_A72_859971
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sysreg_bit_set CORTEX_A72_CPUACTLR_EL1, CORTEX_A72_CPUACTLR_EL1_DIS_INSTR_PREFETCH
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workaround_reset_end cortex_a72, ERRATUM(859971)
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check_erratum_ls cortex_a72, ERRATUM(859971), CPU_REV(0, 3)
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/* Due to the nature of the errata it is applied unconditionally when chosen */
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check_erratum_chosen cortex_a72, ERRATUM(1319367), ERRATA_A72_1319367
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/* erratum workaround is interleaved with generic code */
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add_erratum_entry cortex_a72, ERRATUM(1319367), ERRATA_A72_1319367
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workaround_reset_start cortex_a72, CVE(2017, 5715), WORKAROUND_CVE_2017_5715
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#if IMAGE_BL31
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override_vector_table wa_cve_2017_5715_mmu_vbar
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#endif
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workaround_reset_end cortex_a72, CVE(2017, 5715)
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check_erratum_custom_start cortex_a72, CVE(2017, 5715)
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cpu_check_csv2 x0, 1f
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#if WORKAROUND_CVE_2017_5715
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mov x0, #ERRATA_APPLIES
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#else
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mov x0, #ERRATA_MISSING
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#endif
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ret
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1:
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mov x0, #ERRATA_NOT_APPLIES
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ret
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check_erratum_custom_end cortex_a72, CVE(2017, 5715)
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workaround_reset_start cortex_a72, CVE(2018, 3639), WORKAROUND_CVE_2018_3639
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sysreg_bit_set CORTEX_A72_CPUACTLR_EL1, CORTEX_A72_CPUACTLR_EL1_DIS_LOAD_PASS_STORE
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isb
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dsb sy
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workaround_reset_end cortex_a72, CVE(2018, 3639)
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check_erratum_chosen cortex_a72, CVE(2018, 3639), WORKAROUND_CVE_2018_3639
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workaround_reset_start cortex_a72, CVE(2022, 23960), WORKAROUND_CVE_2022_23960
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#if IMAGE_BL31
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/* Skip installing vector table again if already done for CVE(2017, 5715) */
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/*
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* The Cortex-A72 generic vectors are overridden to apply the
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* mitigation on exception entry from lower ELs for revisions >= r1p0
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* which has CSV2 implemented.
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*/
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adr x0, wa_cve_vbar_cortex_a72
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mrs x1, vbar_el3
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cmp x0, x1
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b.eq 1f
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msr vbar_el3, x0
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1:
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#endif /* IMAGE_BL31 */
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workaround_reset_end cortex_a72, CVE(2022, 23960)
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check_erratum_custom_start cortex_a72, CVE(2022, 23960)
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#if WORKAROUND_CVE_2017_5715 || WORKAROUND_CVE_2022_23960
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cpu_check_csv2 x0, 1f
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mov x0, #ERRATA_APPLIES
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ret
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1:
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#if WORKAROUND_CVE_2022_23960
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mov x0, #ERRATA_APPLIES
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#else
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mov x0, #ERRATA_MISSING
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#endif /* WORKAROUND_CVE_2022_23960 */
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ret
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#endif /* WORKAROUND_CVE_2017_5715 || WORKAROUND_CVE_2022_23960 */
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mov x0, #ERRATA_MISSING
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ret
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check_erratum_custom_end cortex_a72, CVE(2022, 23960)
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cpu_reset_func_start cortex_a72
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/* ---------------------------------------------
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* Enable the SMP bit.
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* ---------------------------------------------
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*/
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sysreg_bit_set CORTEX_A72_ECTLR_EL1, CORTEX_A72_ECTLR_SMP_BIT
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cpu_reset_func_end cortex_a72
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/* ----------------------------------------------------
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* The CPU Ops core power down function for Cortex-A72.
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* ----------------------------------------------------
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*/
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func cortex_a72_core_pwr_dwn
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mov x18, x30
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/* ---------------------------------------------
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* Turn off caches.
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* ---------------------------------------------
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*/
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bl cortex_a72_disable_dcache
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/* ---------------------------------------------
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* Disable the L2 prefetches.
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* ---------------------------------------------
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*/
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bl cortex_a72_disable_l2_prefetch
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/* ---------------------------------------------
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* Disable the load-store hardware prefetcher.
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* ---------------------------------------------
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*/
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bl cortex_a72_disable_hw_prefetcher
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/* ---------------------------------------------
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* Flush L1 caches.
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* ---------------------------------------------
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*/
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mov x0, #DCCISW
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bl dcsw_op_level1
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/* ---------------------------------------------
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* Come out of intra cluster coherency
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* ---------------------------------------------
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*/
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bl cortex_a72_disable_smp
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/* ---------------------------------------------
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* Force the debug interfaces to be quiescent
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* ---------------------------------------------
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*/
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mov x30, x18
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b cortex_a72_disable_ext_debug
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endfunc cortex_a72_core_pwr_dwn
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/* -------------------------------------------------------
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* The CPU Ops cluster power down function for Cortex-A72.
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* -------------------------------------------------------
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*/
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func cortex_a72_cluster_pwr_dwn
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mov x18, x30
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/* ---------------------------------------------
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* Turn off caches.
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* ---------------------------------------------
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*/
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bl cortex_a72_disable_dcache
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/* ---------------------------------------------
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* Disable the L2 prefetches.
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* ---------------------------------------------
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*/
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bl cortex_a72_disable_l2_prefetch
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/* ---------------------------------------------
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* Disable the load-store hardware prefetcher.
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* ---------------------------------------------
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*/
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bl cortex_a72_disable_hw_prefetcher
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#if !SKIP_A72_L1_FLUSH_PWR_DWN
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/* ---------------------------------------------
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* Flush L1 caches.
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* ---------------------------------------------
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*/
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mov x0, #DCCISW
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bl dcsw_op_level1
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#endif
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/* ---------------------------------------------
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* Disable the optional ACP.
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* ---------------------------------------------
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*/
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bl plat_disable_acp
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/* -------------------------------------------------
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* Flush the L2 caches.
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* -------------------------------------------------
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*/
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mov x0, #DCCISW
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bl dcsw_op_level2
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/* ---------------------------------------------
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* Come out of intra cluster coherency
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* ---------------------------------------------
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*/
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bl cortex_a72_disable_smp
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/* ---------------------------------------------
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* Force the debug interfaces to be quiescent
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* ---------------------------------------------
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*/
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mov x30, x18
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b cortex_a72_disable_ext_debug
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endfunc cortex_a72_cluster_pwr_dwn
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/* ---------------------------------------------
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* This function provides cortex_a72 specific
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* register information for crash reporting.
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* It needs to return with x6 pointing to
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* a list of register names in ascii and
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* x8 - x15 having values of registers to be
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* reported.
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* ---------------------------------------------
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*/
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.section .rodata.cortex_a72_regs, "aS"
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cortex_a72_regs: /* The ascii list of register names to be reported */
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.asciz "cpuectlr_el1", "cpumerrsr_el1", "l2merrsr_el1", ""
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func cortex_a72_cpu_reg_dump
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adr x6, cortex_a72_regs
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mrs x8, CORTEX_A72_ECTLR_EL1
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mrs x9, CORTEX_A72_MERRSR_EL1
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mrs x10, CORTEX_A72_L2MERRSR_EL1
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ret
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endfunc cortex_a72_cpu_reg_dump
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declare_cpu_ops_wa cortex_a72, CORTEX_A72_MIDR, \
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cortex_a72_reset_func, \
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check_erratum_cortex_a72_5715, \
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CPU_NO_EXTRA2_FUNC, \
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check_smccc_arch_workaround_3, \
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cortex_a72_core_pwr_dwn, \
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cortex_a72_cluster_pwr_dwn
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