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89dba82dfa
Errata application is painful for performance. For a start, it's done when the core has just come out of reset, which means branch predictors and caches will be empty so a branch to a workaround function must be fetched from memory and that round trip is very slow. Then it also runs with the I-cache off, which means that the loop to iterate over the workarounds must also be fetched from memory on each iteration. We can remove both branches. First, we can simply apply every erratum directly instead of defining a workaround function and jumping to it. Currently, no errata that need to be applied at both reset and runtime, with the same workaround function, exist. If the need arose in future, this should be achievable with a reset + runtime wrapper combo. Then, we can construct a function that applies each erratum linearly instead of looping over the list. If this function is part of the reset function, then the only "far" branches at reset will be for the checker functions. Importantly, this mitigates the slowdown even when an erratum is disabled. The result is ~50% speedup on N1SDP and ~20% on AArch64 Juno on wakeup from PSCI calls that end in powerdown. This is roughly back to the baseline of v2.9, before the errata framework regressed on performance (or a little better). It is important to note that there are other slowdowns since then that remain unknown. Change-Id: Ie4d5288a331b11fd648e5c4a0b652b74160b07b9 Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>
106 lines
3 KiB
ArmAsm
106 lines
3 KiB
ArmAsm
/*
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* Copyright (c) 2020-2025, Arm Limited. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <arch.h>
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#include <asm_macros.S>
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#include <context.h>
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#include <cpu_macros.S>
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#include <cpuamu.h>
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#include <rainier.h>
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/* Hardware handled coherency */
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#if HW_ASSISTED_COHERENCY == 0
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#error "Rainier CPU must be compiled with HW_ASSISTED_COHERENCY enabled"
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#endif
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/* 64-bit only core */
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#if CTX_INCLUDE_AARCH32_REGS == 1
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#error "Rainier CPU supports only AArch64. Compile with CTX_INCLUDE_AARCH32_REGS=0"
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#endif
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cpu_reset_prologue rainier
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/* --------------------------------------------------
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* Disable speculative loads if Rainier supports
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* SSBS.
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*
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* Shall clobber: x0.
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* --------------------------------------------------
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*/
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func rainier_disable_speculative_loads
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/* Check if the PE implements SSBS */
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mrs x0, id_aa64pfr1_el1
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tst x0, #(ID_AA64PFR1_EL1_SSBS_MASK << ID_AA64PFR1_EL1_SSBS_SHIFT)
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b.eq 1f
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/* Disable speculative loads */
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msr SSBS, xzr
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1:
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ret
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endfunc rainier_disable_speculative_loads
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/* Rainier R0P0 is based on Neoverse N1 R4P0. */
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workaround_reset_start rainier, ERRATUM(1868343), ERRATA_N1_1868343
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sysreg_bit_set RAINIER_CPUACTLR_EL1, RAINIER_CPUACTLR_EL1_BIT_13
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workaround_reset_end rainier, ERRATUM(1868343)
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check_erratum_ls rainier, ERRATUM(1868343), CPU_REV(0, 0)
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cpu_reset_func_start rainier
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bl rainier_disable_speculative_loads
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/* Forces all cacheable atomic instructions to be near */
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sysreg_bit_set RAINIER_CPUACTLR2_EL1, RAINIER_CPUACTLR2_EL1_BIT_2
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#if ENABLE_FEAT_AMU
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/* Make sure accesses from EL0/EL1 and EL2 are not trapped to EL3 */
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sysreg_bit_set actlr_el3, RAINIER_ACTLR_AMEN_BIT
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/* Make sure accesses from EL0/EL1 are not trapped to EL2 */
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sysreg_bit_set actlr_el2, RAINIER_ACTLR_AMEN_BIT
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/* Enable group0 counters */
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mov x0, #RAINIER_AMU_GROUP0_MASK
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msr CPUAMCNTENSET_EL0, x0
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#endif
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cpu_reset_func_end rainier
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/* ---------------------------------------------
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* HW will do the cache maintenance while powering down
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* ---------------------------------------------
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*/
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func rainier_core_pwr_dwn
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/* ---------------------------------------------
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* Enable CPU power down bit in power control register
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* ---------------------------------------------
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*/
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sysreg_bit_set RAINIER_CPUPWRCTLR_EL1, RAINIER_CORE_PWRDN_EN_MASK
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isb
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ret
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endfunc rainier_core_pwr_dwn
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/* ---------------------------------------------
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* This function provides Rainier specific
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* register information for crash reporting.
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* It needs to return with x6 pointing to
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* a list of register names in ascii and
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* x8 - x15 having values of registers to be
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* reported.
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* ---------------------------------------------
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*/
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.section .rodata.rainier_regs, "aS"
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rainier_regs: /* The ascii list of register names to be reported */
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.asciz "cpuectlr_el1", ""
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func rainier_cpu_reg_dump
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adr x6, rainier_regs
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mrs x8, RAINIER_CPUECTLR_EL1
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ret
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endfunc rainier_cpu_reg_dump
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declare_cpu_ops rainier, RAINIER_MIDR, \
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rainier_reset_func, \
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rainier_core_pwr_dwn
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