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89dba82dfa
Errata application is painful for performance. For a start, it's done when the core has just come out of reset, which means branch predictors and caches will be empty so a branch to a workaround function must be fetched from memory and that round trip is very slow. Then it also runs with the I-cache off, which means that the loop to iterate over the workarounds must also be fetched from memory on each iteration. We can remove both branches. First, we can simply apply every erratum directly instead of defining a workaround function and jumping to it. Currently, no errata that need to be applied at both reset and runtime, with the same workaround function, exist. If the need arose in future, this should be achievable with a reset + runtime wrapper combo. Then, we can construct a function that applies each erratum linearly instead of looping over the list. If this function is part of the reset function, then the only "far" branches at reset will be for the checker functions. Importantly, this mitigates the slowdown even when an erratum is disabled. The result is ~50% speedup on N1SDP and ~20% on AArch64 Juno on wakeup from PSCI calls that end in powerdown. This is roughly back to the baseline of v2.9, before the errata framework regressed on performance (or a little better). It is important to note that there are other slowdowns since then that remain unknown. Change-Id: Ie4d5288a331b11fd648e5c4a0b652b74160b07b9 Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>
231 lines
7.1 KiB
ArmAsm
231 lines
7.1 KiB
ArmAsm
/*
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* Copyright (c) 2019-2025, Arm Limited. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <arch.h>
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#include <asm_macros.S>
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#include <common/bl_common.h>
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#include <cortex_a78.h>
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#include <cpu_macros.S>
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#include <plat_macros.S>
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#include "wa_cve_2022_23960_bhb_vector.S"
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/* Hardware handled coherency */
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#if HW_ASSISTED_COHERENCY == 0
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#error "cortex_a78 must be compiled with HW_ASSISTED_COHERENCY enabled"
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#endif
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.globl cortex_a78_reset_func
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.globl cortex_a78_core_pwr_dwn
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#if WORKAROUND_CVE_2022_23960
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wa_cve_2022_23960_bhb_vector_table CORTEX_A78_BHB_LOOP_COUNT, cortex_a78
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#endif /* WORKAROUND_CVE_2022_23960 */
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cpu_reset_prologue cortex_a78
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/* Disable hardware page aggregation.Enables mitigation for `CVE-2024-5660` */
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workaround_reset_start cortex_a78, CVE(2024, 5660), WORKAROUND_CVE_2024_5660
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sysreg_bit_set CORTEX_A78_CPUECTLR_EL1, BIT(46)
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workaround_reset_end cortex_a78, CVE(2024, 5660)
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check_erratum_ls cortex_a78, CVE(2024, 5660), CPU_REV(1, 2)
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workaround_reset_start cortex_a78, ERRATUM(1688305), ERRATA_A78_1688305
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sysreg_bit_set CORTEX_A78_ACTLR2_EL1, CORTEX_A78_ACTLR2_EL1_BIT_1
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workaround_reset_end cortex_a78, ERRATUM(1688305)
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check_erratum_ls cortex_a78, ERRATUM(1688305), CPU_REV(1, 0)
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workaround_reset_start cortex_a78, ERRATUM(1821534), ERRATA_A78_1821534
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sysreg_bit_set CORTEX_A78_ACTLR2_EL1, CORTEX_A78_ACTLR2_EL1_BIT_2
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workaround_reset_end cortex_a78, ERRATUM(1821534)
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check_erratum_ls cortex_a78, ERRATUM(1821534), CPU_REV(1, 0)
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workaround_reset_start cortex_a78, ERRATUM(1941498), ERRATA_A78_1941498
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sysreg_bit_set CORTEX_A78_CPUECTLR_EL1, CORTEX_A78_CPUECTLR_EL1_BIT_8
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workaround_reset_end cortex_a78, ERRATUM(1941498)
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check_erratum_ls cortex_a78, ERRATUM(1941498), CPU_REV(1, 1)
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workaround_reset_start cortex_a78, ERRATUM(1951500), ERRATA_A78_1951500
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msr S3_6_c15_c8_0, xzr
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ldr x0, =0x10E3900002
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msr S3_6_c15_c8_2, x0
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ldr x0, =0x10FFF00083
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msr S3_6_c15_c8_3, x0
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ldr x0, =0x2001003FF
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msr S3_6_c15_c8_1, x0
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mov x0, #1
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msr S3_6_c15_c8_0, x0
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ldr x0, =0x10E3800082
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msr S3_6_c15_c8_2, x0
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ldr x0, =0x10FFF00083
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msr S3_6_c15_c8_3, x0
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ldr x0, =0x2001003FF
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msr S3_6_c15_c8_1, x0
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mov x0, #2
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msr S3_6_c15_c8_0, x0
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ldr x0, =0x10E3800200
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msr S3_6_c15_c8_2, x0
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ldr x0, =0x10FFF003E0
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msr S3_6_c15_c8_3, x0
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ldr x0, =0x2001003FF
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msr S3_6_c15_c8_1, x0
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workaround_reset_end cortex_a78, ERRATUM(1951500)
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check_erratum_range cortex_a78, ERRATUM(1951500), CPU_REV(1, 0), CPU_REV(1, 1)
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workaround_reset_start cortex_a78, ERRATUM(1952683), ERRATA_A78_1952683
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ldr x0,=0x5
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msr S3_6_c15_c8_0,x0
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ldr x0,=0xEEE10A10
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msr S3_6_c15_c8_2,x0
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ldr x0,=0xFFEF0FFF
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msr S3_6_c15_c8_3,x0
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ldr x0,=0x0010F000
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msr S3_6_c15_c8_4,x0
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ldr x0,=0x0010F000
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msr S3_6_c15_c8_5,x0
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ldr x0,=0x40000080023ff
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msr S3_6_c15_c8_1,x0
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ldr x0,=0x6
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msr S3_6_c15_c8_0,x0
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ldr x0,=0xEE640F34
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msr S3_6_c15_c8_2,x0
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ldr x0,=0xFFEF0FFF
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msr S3_6_c15_c8_3,x0
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ldr x0,=0x40000080023ff
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msr S3_6_c15_c8_1,x0
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workaround_reset_end cortex_a78, ERRATUM(1952683)
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check_erratum_ls cortex_a78, ERRATUM(1952683), CPU_REV(0, 0)
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workaround_reset_start cortex_a78, ERRATUM(2132060), ERRATA_A78_2132060
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/* Apply the workaround. */
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mrs x1, CORTEX_A78_CPUECTLR_EL1
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mov x0, #CORTEX_A78_CPUECTLR_EL1_PF_MODE_CNSRV
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bfi x1, x0, #CPUECTLR_EL1_PF_MODE_LSB, #CPUECTLR_EL1_PF_MODE_WIDTH
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msr CORTEX_A78_CPUECTLR_EL1, x1
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workaround_reset_end cortex_a78, ERRATUM(2132060)
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check_erratum_ls cortex_a78, ERRATUM(2132060), CPU_REV(1, 2)
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workaround_reset_start cortex_a78, ERRATUM(2242635), ERRATA_A78_2242635
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ldr x0, =0x5
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msr S3_6_c15_c8_0, x0 /* CPUPSELR_EL3 */
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ldr x0, =0x10F600E000
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msr S3_6_c15_c8_2, x0 /* CPUPOR_EL3 */
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ldr x0, =0x10FF80E000
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msr S3_6_c15_c8_3, x0 /* CPUPMR_EL3 */
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ldr x0, =0x80000000003FF
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msr S3_6_c15_c8_1, x0 /* CPUPCR_EL3 */
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workaround_reset_end cortex_a78, ERRATUM(2242635)
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check_erratum_range cortex_a78, ERRATUM(2242635), CPU_REV(1, 0), CPU_REV(1, 2)
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workaround_reset_start cortex_a78, ERRATUM(2376745), ERRATA_A78_2376745
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sysreg_bit_set CORTEX_A78_ACTLR2_EL1, BIT(0)
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workaround_reset_end cortex_a78, ERRATUM(2376745)
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check_erratum_ls cortex_a78, ERRATUM(2376745), CPU_REV(1, 2)
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workaround_reset_start cortex_a78, ERRATUM(2395406), ERRATA_A78_2395406
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sysreg_bit_set CORTEX_A78_ACTLR2_EL1, BIT(40)
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workaround_reset_end cortex_a78, ERRATUM(2395406)
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check_erratum_ls cortex_a78, ERRATUM(2395406), CPU_REV(1, 2)
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workaround_reset_start cortex_a78, ERRATUM(2742426), ERRATA_A78_2742426
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/* Apply the workaround */
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mrs x1, CORTEX_A78_ACTLR5_EL1
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bic x1, x1, #BIT(56)
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orr x1, x1, #BIT(55)
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msr CORTEX_A78_ACTLR5_EL1, x1
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workaround_reset_end cortex_a78, ERRATUM(2742426)
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check_erratum_ls cortex_a78, ERRATUM(2742426), CPU_REV(1, 2)
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workaround_runtime_start cortex_a78, ERRATUM(2772019), ERRATA_A78_2772019
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/* dsb before isb of power down sequence */
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dsb sy
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workaround_runtime_end cortex_a78, ERRATUM(2772019)
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check_erratum_ls cortex_a78, ERRATUM(2772019), CPU_REV(1, 2)
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workaround_reset_start cortex_a78, ERRATUM(2779479), ERRATA_A78_2779479
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sysreg_bit_set CORTEX_A78_ACTLR3_EL1, BIT(47)
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workaround_reset_end cortex_a78, ERRATUM(2779479)
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check_erratum_ls cortex_a78, ERRATUM(2779479), CPU_REV(1, 2)
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workaround_reset_start cortex_a78, CVE(2022, 23960), WORKAROUND_CVE_2022_23960
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#if IMAGE_BL31
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/*
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* The Cortex-X1 generic vectors are overridden to apply errata
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* mitigation on exception entry from lower ELs.
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*/
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override_vector_table wa_cve_vbar_cortex_a78
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#endif /* IMAGE_BL31 */
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workaround_reset_end cortex_a78, CVE(2022, 23960)
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check_erratum_chosen cortex_a78, CVE(2022, 23960), WORKAROUND_CVE_2022_23960
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cpu_reset_func_start cortex_a78
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#if ENABLE_FEAT_AMU
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/* Make sure accesses from EL0/EL1 and EL2 are not trapped to EL3 */
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sysreg_bit_clear actlr_el3, CORTEX_A78_ACTLR_TAM_BIT
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/* Make sure accesses from non-secure EL0/EL1 are not trapped to EL2 */
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sysreg_bit_clear actlr_el2, CORTEX_A78_ACTLR_TAM_BIT
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/* Enable group0 counters */
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mov x0, #CORTEX_A78_AMU_GROUP0_MASK
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msr CPUAMCNTENSET0_EL0, x0
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/* Enable group1 counters */
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mov x0, #CORTEX_A78_AMU_GROUP1_MASK
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msr CPUAMCNTENSET1_EL0, x0
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#endif
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cpu_reset_func_end cortex_a78
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/* ---------------------------------------------
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* HW will do the cache maintenance while powering down
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* ---------------------------------------------
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*/
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func cortex_a78_core_pwr_dwn
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sysreg_bit_set CORTEX_A78_CPUPWRCTLR_EL1, CORTEX_A78_CPUPWRCTLR_EL1_CORE_PWRDN_EN_BIT
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apply_erratum cortex_a78, ERRATUM(2772019), ERRATA_A78_2772019, NO_GET_CPU_REV
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isb
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ret
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endfunc cortex_a78_core_pwr_dwn
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/* ---------------------------------------------
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* This function provides cortex_a78 specific
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* register information for crash reporting.
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* It needs to return with x6 pointing to
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* a list of register names in ascii and
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* x8 - x15 having values of registers to be
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* reported.
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* ---------------------------------------------
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*/
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.section .rodata.cortex_a78_regs, "aS"
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cortex_a78_regs: /* The ascii list of register names to be reported */
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.asciz "cpuectlr_el1", ""
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func cortex_a78_cpu_reg_dump
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adr x6, cortex_a78_regs
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mrs x8, CORTEX_A78_CPUECTLR_EL1
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ret
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endfunc cortex_a78_cpu_reg_dump
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declare_cpu_ops cortex_a78, CORTEX_A78_MIDR, \
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cortex_a78_reset_func, \
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cortex_a78_core_pwr_dwn
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