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Errata application is painful for performance. For a start, it's done when the core has just come out of reset, which means branch predictors and caches will be empty so a branch to a workaround function must be fetched from memory and that round trip is very slow. Then it also runs with the I-cache off, which means that the loop to iterate over the workarounds must also be fetched from memory on each iteration. We can remove both branches. First, we can simply apply every erratum directly instead of defining a workaround function and jumping to it. Currently, no errata that need to be applied at both reset and runtime, with the same workaround function, exist. If the need arose in future, this should be achievable with a reset + runtime wrapper combo. Then, we can construct a function that applies each erratum linearly instead of looping over the list. If this function is part of the reset function, then the only "far" branches at reset will be for the checker functions. Importantly, this mitigates the slowdown even when an erratum is disabled. The result is ~50% speedup on N1SDP and ~20% on AArch64 Juno on wakeup from PSCI calls that end in powerdown. This is roughly back to the baseline of v2.9, before the errata framework regressed on performance (or a little better). It is important to note that there are other slowdowns since then that remain unknown. Change-Id: Ie4d5288a331b11fd648e5c4a0b652b74160b07b9 Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>
99 lines
2.6 KiB
C
99 lines
2.6 KiB
C
/*
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* Copyright (c) 2017-2025, Arm Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef ERRATA_H
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#define ERRATA_H
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#include <lib/cpus/cpu_ops.h>
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#define ERRATUM_CHECK_FUNC_SIZE CPU_WORD_SIZE
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#define ERRATUM_ID_SIZE 4
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#define ERRATUM_CVE_SIZE 2
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#define ERRATUM_CHOSEN_SIZE 1
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#define ERRATUM_ALIGNMENT_SIZE 1
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#define ERRATUM_CHECK_FUNC 0
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#define ERRATUM_ID ERRATUM_CHECK_FUNC + ERRATUM_CHECK_FUNC_SIZE
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#define ERRATUM_CVE ERRATUM_ID + ERRATUM_ID_SIZE
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#define ERRATUM_CHOSEN ERRATUM_CVE + ERRATUM_CVE_SIZE
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#define ERRATUM_ALIGNMENT ERRATUM_CHOSEN + ERRATUM_CHOSEN_SIZE
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#define ERRATUM_ENTRY_SIZE ERRATUM_ALIGNMENT + ERRATUM_ALIGNMENT_SIZE
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/* Errata status */
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#define ERRATA_NOT_APPLIES 0
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#define ERRATA_APPLIES 1
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#define ERRATA_MISSING 2
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#ifndef __ASSEMBLER__
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#include <lib/cassert.h>
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void print_errata_status(void);
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/*
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* NOTE that this structure will be different on AArch32 and AArch64. The
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* uintptr_t will reflect the change and the alignment will be correct in both.
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*/
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struct erratum_entry {
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uintptr_t (*check_func)(uint64_t cpu_rev);
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/* Will fit CVEs with up to 10 character in the ID field */
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uint32_t id;
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/* Denote CVEs with their year or errata with 0 */
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uint16_t cve;
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uint8_t chosen;
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uint8_t _alignment;
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} __packed;
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CASSERT(sizeof(struct erratum_entry) == ERRATUM_ENTRY_SIZE,
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assert_erratum_entry_asm_c_different_sizes);
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/*
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* Runtime errata helpers.
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*/
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#if ERRATA_A75_764081
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bool errata_a75_764081_applies(void);
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#else
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static inline bool errata_a75_764081_applies(void)
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{
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return false;
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}
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#endif
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#if ERRATA_A520_2938996 || ERRATA_X4_2726228
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unsigned int check_if_affected_core(void);
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#endif
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int check_wa_cve_2024_7881(void);
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bool errata_ich_vmcr_el2_applies(void);
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#else
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/*
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* errata framework macro helpers
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*
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* NOTE an erratum and CVE id could clash. However, both numbers are very large
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* and the probablity is minuscule. Working around this makes code very
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* complicated and extremely difficult to read so it is not considered. In the
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* unlikely event that this does happen, prepending the CVE id with a 0 should
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* resolve the conflict
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*/
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#define ERRATUM(id) 0, id
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#define CVE(year, id) year, id
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#define NO_ISB 1
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#define NO_ASSERT 0
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#define NO_APPLY_AT_RESET 0
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#define APPLY_AT_RESET 1
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#define GET_CPU_REV 1
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#define NO_GET_CPU_REV 0
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/* useful for errata that end up always being worked around */
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#define ERRATUM_ALWAYS_CHOSEN 1
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#endif /* __ASSEMBLER__ */
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/* Macro to get CPU revision code for checking errata version compatibility. */
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#define CPU_REV(r, p) ((r << 4) | p)
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#endif /* ERRATA_H */
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