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89dba82dfa
Errata application is painful for performance. For a start, it's done when the core has just come out of reset, which means branch predictors and caches will be empty so a branch to a workaround function must be fetched from memory and that round trip is very slow. Then it also runs with the I-cache off, which means that the loop to iterate over the workarounds must also be fetched from memory on each iteration. We can remove both branches. First, we can simply apply every erratum directly instead of defining a workaround function and jumping to it. Currently, no errata that need to be applied at both reset and runtime, with the same workaround function, exist. If the need arose in future, this should be achievable with a reset + runtime wrapper combo. Then, we can construct a function that applies each erratum linearly instead of looping over the list. If this function is part of the reset function, then the only "far" branches at reset will be for the checker functions. Importantly, this mitigates the slowdown even when an erratum is disabled. The result is ~50% speedup on N1SDP and ~20% on AArch64 Juno on wakeup from PSCI calls that end in powerdown. This is roughly back to the baseline of v2.9, before the errata framework regressed on performance (or a little better). It is important to note that there are other slowdowns since then that remain unknown. Change-Id: Ie4d5288a331b11fd648e5c4a0b652b74160b07b9 Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>
161 lines
5.3 KiB
ArmAsm
161 lines
5.3 KiB
ArmAsm
/*
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* Copyright (c) 2019-2025, Arm Limited. All rights reserved.
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* Copyright (c) 2021-2023, NVIDIA Corporation. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <arch.h>
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#include <asm_macros.S>
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#include <common/bl_common.h>
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#include <cortex_a78_ae.h>
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#include <cpu_macros.S>
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#include <plat_macros.S>
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#include "wa_cve_2022_23960_bhb_vector.S"
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/* Hardware handled coherency */
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#if HW_ASSISTED_COHERENCY == 0
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#error "cortex_a78_ae must be compiled with HW_ASSISTED_COHERENCY enabled"
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#endif
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#if WORKAROUND_CVE_2022_23960
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wa_cve_2022_23960_bhb_vector_table CORTEX_A78_AE_BHB_LOOP_COUNT, cortex_a78_ae
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#endif /* WORKAROUND_CVE_2022_23960 */
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cpu_reset_prologue cortex_a78_ae
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/* Disable hardware page aggregation. Enables mitigation for `CVE-2024-5660` */
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workaround_reset_start cortex_a78_ae, CVE(2024, 5660), WORKAROUND_CVE_2024_5660
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sysreg_bit_set CORTEX_A78_AE_CPUECTLR_EL1, BIT(46)
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workaround_reset_end cortex_a78_ae, CVE(2024, 5660)
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check_erratum_ls cortex_a78_ae, CVE(2024, 5660), CPU_REV(0, 3)
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workaround_reset_start cortex_a78_ae, ERRATUM(1941500), ERRATA_A78_AE_1941500
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sysreg_bit_set CORTEX_A78_AE_CPUECTLR_EL1, CORTEX_A78_AE_CPUECTLR_EL1_BIT_8
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workaround_reset_end cortex_a78_ae, ERRATUM(1941500)
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check_erratum_ls cortex_a78_ae, ERRATUM(1941500), CPU_REV(0, 1)
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workaround_reset_start cortex_a78_ae, ERRATUM(1951502), ERRATA_A78_AE_1951502
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msr S3_6_c15_c8_0, xzr
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ldr x0, =0x10E3900002
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msr S3_6_c15_c8_2, x0
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ldr x0, =0x10FFF00083
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msr S3_6_c15_c8_3, x0
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ldr x0, =0x2001003FF
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msr S3_6_c15_c8_1, x0
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mov x0, #1
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msr S3_6_c15_c8_0, x0
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ldr x0, =0x10E3800082
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msr S3_6_c15_c8_2, x0
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ldr x0, =0x10FFF00083
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msr S3_6_c15_c8_3, x0
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ldr x0, =0x2001003FF
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msr S3_6_c15_c8_1, x0
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mov x0, #2
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msr S3_6_c15_c8_0, x0
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ldr x0, =0x10E3800200
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msr S3_6_c15_c8_2, x0
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ldr x0, =0x10FFF003E0
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msr S3_6_c15_c8_3, x0
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ldr x0, =0x2001003FF
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msr S3_6_c15_c8_1, x0
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workaround_reset_end cortex_a78_ae, ERRATUM(1951502)
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check_erratum_ls cortex_a78_ae, ERRATUM(1951502), CPU_REV(0, 1)
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workaround_reset_start cortex_a78_ae, ERRATUM(2376748), ERRATA_A78_AE_2376748
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/* -------------------------------------------------------
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* Set CPUACTLR2_EL1[0] to 1 to force PLDW/PFRM ST to
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* behave like PLD/PRFM LD and not cause invalidations to
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* other PE caches. There might be a small performance
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* degradation to this workaround for certain workloads
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* that share data.
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* -------------------------------------------------------
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*/
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sysreg_bit_set CORTEX_A78_AE_ACTLR2_EL1, CORTEX_A78_AE_ACTLR2_EL1_BIT_0
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workaround_reset_end cortex_a78_ae, ERRATUM(2376748)
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check_erratum_ls cortex_a78_ae, ERRATUM(2376748), CPU_REV(0, 2)
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workaround_reset_start cortex_a78_ae, ERRATUM(2395408), ERRATA_A78_AE_2395408
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/* --------------------------------------------------------
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* Disable folding of demand requests into older prefetches
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* with L2 miss requests outstanding by setting the
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* CPUACTLR2_EL1[40] to 1.
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* --------------------------------------------------------
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*/
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sysreg_bit_set CORTEX_A78_AE_ACTLR2_EL1, CORTEX_A78_AE_ACTLR2_EL1_BIT_40
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workaround_reset_end cortex_a78_ae, ERRATUM(2395408)
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check_erratum_ls cortex_a78_ae, ERRATUM(2395408), CPU_REV(0, 1)
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workaround_reset_start cortex_a78_ae, CVE(2022, 23960), WORKAROUND_CVE_2022_23960
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#if IMAGE_BL31
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/*
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* The Cortex-A78AE generic vectors are overridden to apply errata
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* mitigation on exception entry from lower ELs.
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*/
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override_vector_table wa_cve_vbar_cortex_a78_ae
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#endif /* IMAGE_BL31 */
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workaround_reset_end cortex_a78_ae, CVE(2022, 23960)
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check_erratum_chosen cortex_a78_ae, CVE(2022, 23960), WORKAROUND_CVE_2022_23960
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cpu_reset_func_start cortex_a78_ae
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#if ENABLE_FEAT_AMU
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/* Make sure accesses from EL0/EL1 and EL2 are not trapped to EL3 */
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sysreg_bit_clear actlr_el3, CORTEX_A78_ACTLR_TAM_BIT
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/* Make sure accesses from non-secure EL0/EL1 are not trapped to EL2 */
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sysreg_bit_clear actlr_el2, CORTEX_A78_ACTLR_TAM_BIT
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/* Enable group0 counters */
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mov x0, #CORTEX_A78_AMU_GROUP0_MASK
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msr CPUAMCNTENSET0_EL0, x0
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/* Enable group1 counters */
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mov x0, #CORTEX_A78_AMU_GROUP1_MASK
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msr CPUAMCNTENSET1_EL0, x0
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#endif
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cpu_reset_func_end cortex_a78_ae
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/* -------------------------------------------------------
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* HW will do the cache maintenance while powering down
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* -------------------------------------------------------
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*/
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func cortex_a78_ae_core_pwr_dwn
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/* -------------------------------------------------------
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* Enable CPU power down bit in power control register
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* -------------------------------------------------------
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*/
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sysreg_bit_set CORTEX_A78_CPUPWRCTLR_EL1, CORTEX_A78_CPUPWRCTLR_EL1_CORE_PWRDN_EN_BIT
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isb
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ret
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endfunc cortex_a78_ae_core_pwr_dwn
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/* -------------------------------------------------------
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* This function provides cortex_a78_ae specific
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* register information for crash reporting.
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* It needs to return with x6 pointing to
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* a list of register names in ascii and
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* x8 - x15 having values of registers to be
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* reported.
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* -------------------------------------------------------
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*/
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.section .rodata.cortex_a78_ae_regs, "aS"
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cortex_a78_ae_regs: /* The ascii list of register names to be reported */
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.asciz "cpuectlr_el1", ""
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func cortex_a78_ae_cpu_reg_dump
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adr x6, cortex_a78_ae_regs
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mrs x8, CORTEX_A78_CPUECTLR_EL1
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ret
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endfunc cortex_a78_ae_cpu_reg_dump
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declare_cpu_ops cortex_a78_ae, CORTEX_A78_AE_MIDR, \
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cortex_a78_ae_reset_func, \
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cortex_a78_ae_core_pwr_dwn
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