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89dba82dfa
Errata application is painful for performance. For a start, it's done when the core has just come out of reset, which means branch predictors and caches will be empty so a branch to a workaround function must be fetched from memory and that round trip is very slow. Then it also runs with the I-cache off, which means that the loop to iterate over the workarounds must also be fetched from memory on each iteration. We can remove both branches. First, we can simply apply every erratum directly instead of defining a workaround function and jumping to it. Currently, no errata that need to be applied at both reset and runtime, with the same workaround function, exist. If the need arose in future, this should be achievable with a reset + runtime wrapper combo. Then, we can construct a function that applies each erratum linearly instead of looping over the list. If this function is part of the reset function, then the only "far" branches at reset will be for the checker functions. Importantly, this mitigates the slowdown even when an erratum is disabled. The result is ~50% speedup on N1SDP and ~20% on AArch64 Juno on wakeup from PSCI calls that end in powerdown. This is roughly back to the baseline of v2.9, before the errata framework regressed on performance (or a little better). It is important to note that there are other slowdowns since then that remain unknown. Change-Id: Ie4d5288a331b11fd648e5c4a0b652b74160b07b9 Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>
77 lines
2.2 KiB
ArmAsm
77 lines
2.2 KiB
ArmAsm
/*
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* Copyright (c) 2023-2025, Arm Limited. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <arch.h>
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#include <asm_macros.S>
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#include <common/bl_common.h>
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#include <neoverse_n3.h>
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#include <cpu_macros.S>
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#include <plat_macros.S>
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/* Hardware handled coherency */
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#if HW_ASSISTED_COHERENCY == 0
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#error "Neoverse-N3 must be compiled with HW_ASSISTED_COHERENCY enabled"
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#endif
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/* 64-bit only core */
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#if CTX_INCLUDE_AARCH32_REGS == 1
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#error "Neoverse-N3 supports only AArch64. Compile with CTX_INCLUDE_AARCH32_REGS=0"
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#endif
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cpu_reset_prologue neoverse_n3
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.global check_erratum_neoverse_n3_3699563
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add_erratum_entry neoverse_n3, ERRATUM(3699563), ERRATA_N3_3699563
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check_erratum_ls neoverse_n3, ERRATUM(3699563), CPU_REV(0, 0)
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cpu_reset_func_start neoverse_n3
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/* Disable speculative loads */
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msr SSBS, xzr
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#if NEOVERSE_Nx_EXTERNAL_LLC
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/* Some systems may have External LLC, core needs to be made aware */
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sysreg_bit_set NEOVERSE_N3_CPUECTLR_EL1, NEOVERSE_N3_CPUECTLR_EL1_EXTLLC_BIT
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#endif
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cpu_reset_func_end neoverse_n3
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/* ----------------------------------------------------
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* HW will do the cache maintenance while powering down
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* ----------------------------------------------------
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*/
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func neoverse_n3_core_pwr_dwn
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/* ---------------------------------------------------
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* Enable CPU power down bit in power control register
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* ---------------------------------------------------
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*/
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sysreg_bit_set NEOVERSE_N3_CPUPWRCTLR_EL1, NEOVERSE_N3_CPUPWRCTLR_EL1_CORE_PWRDN_BIT
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isb
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ret
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endfunc neoverse_n3_core_pwr_dwn
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/* ---------------------------------------------
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* This function provides Neoverse-N3 specific
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* register information for crash reporting.
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* It needs to return with x6 pointing to
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* a list of register names in ascii and
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* x8 - x15 having values of registers to be
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* reported.
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* ---------------------------------------------
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*/
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.section .rodata.neoverse_n3_regs, "aS"
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neoverse_n3_regs: /* The ascii list of register names to be reported */
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.asciz "cpuectlr_el1", ""
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func neoverse_n3_cpu_reg_dump
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adr x6, neoverse_n3_regs
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mrs x8, NEOVERSE_N3_CPUECTLR_EL1
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ret
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endfunc neoverse_n3_cpu_reg_dump
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declare_cpu_ops neoverse_n3, NEOVERSE_N3_MIDR, \
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neoverse_n3_reset_func, \
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neoverse_n3_core_pwr_dwn
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