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89dba82dfa
Errata application is painful for performance. For a start, it's done when the core has just come out of reset, which means branch predictors and caches will be empty so a branch to a workaround function must be fetched from memory and that round trip is very slow. Then it also runs with the I-cache off, which means that the loop to iterate over the workarounds must also be fetched from memory on each iteration. We can remove both branches. First, we can simply apply every erratum directly instead of defining a workaround function and jumping to it. Currently, no errata that need to be applied at both reset and runtime, with the same workaround function, exist. If the need arose in future, this should be achievable with a reset + runtime wrapper combo. Then, we can construct a function that applies each erratum linearly instead of looping over the list. If this function is part of the reset function, then the only "far" branches at reset will be for the checker functions. Importantly, this mitigates the slowdown even when an erratum is disabled. The result is ~50% speedup on N1SDP and ~20% on AArch64 Juno on wakeup from PSCI calls that end in powerdown. This is roughly back to the baseline of v2.9, before the errata framework regressed on performance (or a little better). It is important to note that there are other slowdowns since then that remain unknown. Change-Id: Ie4d5288a331b11fd648e5c4a0b652b74160b07b9 Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>
178 lines
5.8 KiB
ArmAsm
178 lines
5.8 KiB
ArmAsm
/*
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* Copyright (c) 2022-2025, Arm Limited. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <arch.h>
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#include <asm_macros.S>
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#include <common/bl_common.h>
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#include <cortex_x4.h>
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#include <cpu_macros.S>
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#include <plat_macros.S>
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#include "wa_cve_2022_23960_bhb_vector.S"
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/* Hardware handled coherency */
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#if HW_ASSISTED_COHERENCY == 0
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#error "Cortex X4 must be compiled with HW_ASSISTED_COHERENCY enabled"
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#endif
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/* 64-bit only core */
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#if CTX_INCLUDE_AARCH32_REGS == 1
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#error "Cortex X4 supports only AArch64. Compile with CTX_INCLUDE_AARCH32_REGS=0"
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#endif
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cpu_reset_prologue cortex_x4
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.global check_erratum_cortex_x4_2726228
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.global check_erratum_cortex_x4_3701758
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#if WORKAROUND_CVE_2022_23960
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wa_cve_2022_23960_bhb_vector_table CORTEX_X4_BHB_LOOP_COUNT, cortex_x4
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#endif /* WORKAROUND_CVE_2022_23960 */
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workaround_runtime_start cortex_x4, ERRATUM(2726228), ERRATA_X4_2726228, CORTEX_X4_MIDR
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workaround_runtime_end cortex_x4, ERRATUM(2726228)
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check_erratum_ls cortex_x4, ERRATUM(2726228), CPU_REV(0, 1)
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/* Disable hardware page aggregation. Enables mitigation for `CVE-2024-5660` */
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workaround_reset_start cortex_x4, CVE(2024, 5660), WORKAROUND_CVE_2024_5660
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sysreg_bit_set CORTEX_X4_CPUECTLR_EL1, BIT(46)
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workaround_reset_end cortex_x4, CVE(2024, 5660)
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check_erratum_ls cortex_x4, CVE(2024, 5660), CPU_REV(0, 2)
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workaround_runtime_start cortex_x4, ERRATUM(2740089), ERRATA_X4_2740089
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/* dsb before isb of power down sequence */
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dsb sy
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workaround_runtime_end cortex_x4, ERRATUM(2740089)
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check_erratum_ls cortex_x4, ERRATUM(2740089), CPU_REV(0, 1)
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workaround_reset_start cortex_x4, ERRATUM(2763018), ERRATA_X4_2763018
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sysreg_bit_set CORTEX_X4_CPUACTLR3_EL1, BIT(47)
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workaround_reset_end cortex_x4, ERRATUM(2763018)
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check_erratum_ls cortex_x4, ERRATUM(2763018), CPU_REV(0, 1)
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workaround_reset_start cortex_x4, ERRATUM(2816013), ERRATA_X4_2816013
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mrs x1, id_aa64pfr1_el1
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ubfx x2, x1, ID_AA64PFR1_EL1_MTE_SHIFT, #4
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cbz x2, #1f
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sysreg_bit_set CORTEX_X4_CPUACTLR5_EL1, BIT(14)
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1:
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workaround_reset_end cortex_x4, ERRATUM(2816013)
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check_erratum_ls cortex_x4, ERRATUM(2816013), CPU_REV(0, 1)
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workaround_reset_start cortex_x4, ERRATUM(2897503), ERRATA_X4_2897503
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sysreg_bit_set CORTEX_X4_CPUACTLR4_EL1, BIT(8)
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workaround_reset_end cortex_x4, ERRATUM(2897503)
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check_erratum_ls cortex_x4, ERRATUM(2897503), CPU_REV(0, 1)
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workaround_reset_start cortex_x4, ERRATUM(2923985), ERRATA_X4_2923985
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sysreg_bit_set CORTEX_X4_CPUACTLR4_EL1, (BIT(11) | BIT(10))
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workaround_reset_end cortex_x4, ERRATUM(2923985)
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check_erratum_ls cortex_x4, ERRATUM(2923985), CPU_REV(0, 1)
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workaround_reset_start cortex_x4, ERRATUM(2957258), ERRATA_X4_2957258
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/* Add ISB before MRS reads of MPIDR_EL1/MIDR_EL1 */
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ldr x0, =0x1
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msr S3_6_c15_c8_0, x0 /* msr CPUPSELR_EL3, X0 */
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ldr x0, =0xd5380000
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msr S3_6_c15_c8_2, x0 /* msr CPUPOR_EL3, X0 */
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ldr x0, =0xFFFFFF40
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msr S3_6_c15_c8_3,x0 /* msr CPUPMR_EL3, X0 */
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ldr x0, =0x000080010033f
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msr S3_6_c15_c8_1, x0 /* msr CPUPCR_EL3, X0 */
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isb
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workaround_reset_end cortex_x4, ERRATUM(2957258)
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check_erratum_ls cortex_x4, ERRATUM(2957258), CPU_REV(0, 1)
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workaround_reset_start cortex_x4, ERRATUM(3076789), ERRATA_X4_3076789
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sysreg_bit_set CORTEX_X4_CPUACTLR3_EL1, BIT(14)
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sysreg_bit_set CORTEX_X4_CPUACTLR3_EL1, BIT(13)
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sysreg_bit_set CORTEX_X4_CPUACTLR_EL1, BIT(52)
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workaround_reset_end cortex_x4, ERRATUM(3076789)
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check_erratum_ls cortex_x4, ERRATUM(3076789), CPU_REV(0, 1)
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workaround_reset_start cortex_x4, CVE(2022, 23960), WORKAROUND_CVE_2022_23960
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#if IMAGE_BL31
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/*
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* The Cortex X4 generic vectors are overridden to apply errata
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* mitigation on exception entry from lower ELs.
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*/
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override_vector_table wa_cve_vbar_cortex_x4
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#endif /* IMAGE_BL31 */
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workaround_reset_end cortex_x4, CVE(2022, 23960)
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check_erratum_chosen cortex_x4, CVE(2022, 23960), WORKAROUND_CVE_2022_23960
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workaround_reset_start cortex_x4, CVE(2024, 7881), WORKAROUND_CVE_2024_7881
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/* ---------------------------------
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* Sets BIT41 of CPUACTLR6_EL1 which
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* disables L1 Data cache prefetcher
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* ---------------------------------
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*/
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sysreg_bit_set CORTEX_X4_CPUACTLR6_EL1, BIT(41)
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workaround_reset_end cortex_x4, CVE(2024, 7881)
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check_erratum_chosen cortex_x4, CVE(2024, 7881), WORKAROUND_CVE_2024_7881
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add_erratum_entry cortex_x4, ERRATUM(3701758), ERRATA_X4_3701758
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check_erratum_ls cortex_x4, ERRATUM(3701758), CPU_REV(0, 3)
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cpu_reset_func_start cortex_x4
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/* Disable speculative loads */
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msr SSBS, xzr
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cpu_reset_func_end cortex_x4
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/* ----------------------------------------------------
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* HW will do the cache maintenance while powering down
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* ----------------------------------------------------
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*/
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func cortex_x4_core_pwr_dwn
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/* ---------------------------------------------------
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* Enable CPU power down bit in power control register
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* ---------------------------------------------------
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*/
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sysreg_bit_set CORTEX_X4_CPUPWRCTLR_EL1, CORTEX_X4_CPUPWRCTLR_EL1_CORE_PWRDN_BIT
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apply_erratum cortex_x4, ERRATUM(2740089), ERRATA_X4_2740089, NO_GET_CPU_REV
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isb
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ret
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endfunc cortex_x4_core_pwr_dwn
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/* ---------------------------------------------
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* This function provides Cortex X4-specific
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* register information for crash reporting.
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* It needs to return with x6 pointing to
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* a list of register names in ascii and
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* x8 - x15 having values of registers to be
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* reported.
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* ---------------------------------------------
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*/
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.section .rodata.cortex_x4_regs, "aS"
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cortex_x4_regs: /* The ascii list of register names to be reported */
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.asciz "cpuectlr_el1", ""
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func cortex_x4_cpu_reg_dump
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adr x6, cortex_x4_regs
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mrs x8, CORTEX_X4_CPUECTLR_EL1
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ret
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endfunc cortex_x4_cpu_reg_dump
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declare_cpu_ops_wa_4 cortex_x4, CORTEX_X4_MIDR, \
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cortex_x4_reset_func, \
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CPU_NO_EXTRA1_FUNC, \
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CPU_NO_EXTRA2_FUNC, \
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CPU_NO_EXTRA3_FUNC, \
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check_erratum_cortex_x4_7881, \
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cortex_x4_core_pwr_dwn
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