Refactor `arm_bl2_early_platform_setup` to accept generic u_register_t
values, enabling support for firmware handoff boot arguments in
common code. This simplifies the interface for early platform setup.
Signed-off-by: Jayanth Dodderi Chidanand <jayanthdodderi.chidanand@arm.com>
Change-Id: Ie0dbe4d32bbef22bd185fdafe50091a2ea5f550f
This patch introduces Firmware Handoff support for Arm based
platforms listed under Firmware_Handoff specification.
[https://firmwarehandoff.github.io/firmware_handoff/main/transfer_list.html]
Signed-off-by: Jayanth Dodderi Chidanand <jayanthdodderi.chidanand@arm.com>
Change-Id: Ie3f30ffe38f809db907b663a8dbf1e48944ec690
Report `FFA_MEM_PERM_GET` and `FFA_MEM_PERM_SET` supported to secure
world instances.
Signed-off-by: Karl Meakin <karl.meakin@arm.com>
Change-Id: I90e6b0ab601ae1142b419cacfa56109c183ab640
For some unknown reasons I did miss this '+' which does not make
sense when I submitted the former commit. We all did miss
it during codre reviews, sorry for the confusion. I do not understand
how it happened, late commits -> stupid issues.
Revert and fix: 634c7d81 fix create_pbl buildroot build
Wall -Werror -pedantic -std=c99 -O2 -DVERSION='"v2.12.0(release):master"' -D_GNU_SOURCE -D_XOPEN_SOURCE=700 -c -o create_pbl.o create_pbl.c
make[3]: Wall: No such file or directory
Change-Id: I1e17e4793061966ce5fa5e0c122914bfaed27952
Signed-off-by: Vincent Jardin <vjardin@free.fr>
* changes:
fix(psci): add const qualifier
fix(el3-runtime): add const qualifier
fix(bl31): add const qualifier
fix(console): typecast expressions to match data type
fix(arm-drivers): typecast expressions to match data type
fix(arm-drivers): align essential type categories
fix(arm-drivers): typecast expression to match data type
Some platforms do not support FEAT_MEC. Hence, they do not provide
an interface to update the update of the key corresponding to a
MECID.
This patch adds a condition in order to verify FEAT_MEC is present
before calling the corresponding platform hook, thus preventing it
from being called when the platform does not support the feature.
Change-Id: Ib1eb9e42f475e27ec31529569e888b93b207148c
Signed-off-by: Juan Pablo Conde <juanpablo.conde@arm.com>
* changes:
fix(versal): handle invalid entry point in cpu hotplug scenario
fix(versal-net): handle invalid entry point in cpu hotplug scenario
fix(zynqmp): handle invalid entry point in cpu hotplug scenario
Invalid addresses are from 2G-4G and also address where TF-A is.
Change-Id: I3d07808821da3bdd46be819ad829cb284f9d53d3
Signed-off-by: Maheedhar Bollapalli <maheedharsai.bollapalli@amd.com>
Invalid addresses are from 2G-4G and also address where TF-A is.
Change-Id: I153d26bd92ea26efcd7f236e2f1d89c3e5442ba4
Signed-off-by: Maheedhar Bollapalli <maheedharsai.bollapalli@amd.com>
Invalid addresses are from 2G-4G and also address where TF-A is.
Change-Id: Iedb817a2f9667b7d0b9a3ac03891a5b93295bf87
Signed-off-by: Maheedhar Bollapalli <maheedharsai.bollapalli@amd.com>
The compiler complains that it may be used unitialised. Give it some
confidence that won't be the case.
Change-Id: I14bddd48e4b205121415025175f157b92a89aa26
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>
- Define information structures for SMMU, root complex,
root port and BDF mappings.
- Add entries for SMMU and PCIe root complexes to Boot manifest.
- Update RMMD_MANIFEST_VERSION_MINOR from 4 to 5.
Change-Id: I0a76dc18edbaaff40116f376aeb56c750d57c7c1
Signed-off-by: AlexeiFedorov <Alexei.Fedorov@arm.com>
* changes:
refactor(arm): simplify early platform setup functions
feat(bl32): enable r3 usage for boot args
feat(handoff): add lib to sp-min sources
feat(handoff): add 32-bit variant of SRAM layout
feat(handoff): add 32-bit variant of ep info
fix(aarch32): avoid using r12 to store boot params
fix(arm): reinit secure and non-secure tls
refactor(handoff): downgrade error messages
* changes:
chore(cpus): rearrange the errata and cve order in Neoverse-N2
chore(cpus): rearrange cve in order in Cortex-X1
chore(cpus): fix cve order in Neoverse-V1
chore(cpus): fix cve order in Cortex-X2
chore(cpus): fix cve order in Cortex-A78C
chore(cpus): fix cve order in Cortex-A78_AE
chore(cpus): fix cve order in Cortex-A78
chore(cpus): fix cve order in Cortex-A77
Patch sorts the errata IDs in ascending order and the
CVE's in ascending order based on the year and index
for CPU Cortex-X4.
Change-Id: Ic304c2f68e7d0b96bbb30760696b7bceabe1ae2d
Signed-off-by: Sona Mathew <sonarebecca.mathew@arm.com>
Patch sorts the errata IDs in ascending order and the
CVE-2024-5660 in order based on the year and index
for Cortex-X3.
Change-Id: I2a4baebe0c3133528c089d999bdffa8c992f4989
Signed-off-by: Sona Mathew <sonarebecca.mathew@arm.com>
Patch rearranges CVE-2024-5660 in order based on
the year and index for Neoverse-V2.
Change-Id: I092a93ef3299fd733abae9c462c019f94d881413
Signed-off-by: Sona Mathew <sonarebecca.mathew@arm.com>
Patch sorts the errata IDs in ascending order and the
CVE's in ascending order based on the year and index
for CPU Neoverse N2.
Change-Id: Ieb4a8ab0030ea4e83efdef86a0ff1e2990b3e0dd
Signed-off-by: Sona Mathew <sonarebecca.mathew@arm.com>
Patch sorts the errata IDs in ascending order and the CVE's
in ascending order based on the year and index for Neoverse-V3.
Change-Id: I108eb2896e24c135d56e5096289766d777b48b48
Signed-off-by: Sona Mathew <sonarebecca.mathew@arm.com>
Patch sorts the errata IDs in ascending order and the
CVE's in ascending order based on the year and index
for CPU Cortex-A710.
Change-Id: Ie7c2b77879f8fa5abb77204678e09cc759b10278
Signed-off-by: Sona Mathew <sonarebecca.mathew@arm.com>
Patch rearranges CVE-2024-5660 in ascending order based on
the year and index for Cortex X1.
Change-Id: I0c4206e38f09b1f88ee95e8ce69d7e13b8a9bb2d
Signed-off-by: Sona Mathew <sonarebecca.mathew@arm.com>
This patch rearranges CVE-2024-5660 apply order in Neoverse-V1.
Signed-off-by: Arvind Ram Prakash <arvind.ramprakash@arm.com>
Change-Id: Ice0b1c6efa913f88522fb33182b9cdc0e7723988
This patch rearranges CVE-2024-5660, erratum 2313941
and 3701772 apply order in Cortex-X2.
Signed-off-by: Arvind Ram Prakash <arvind.ramprakash@arm.com>
Change-Id: Ie74d7232a14f3cdd14c4d0ffb1ee91b537c491ea
This patch rearranges CVE-2024-5660 apply order in Cortex-A78C.
Signed-off-by: Arvind Ram Prakash <arvind.ramprakash@arm.com>
Change-Id: I326be1da279bd34df8667f7e957fb4a2c6913ab9
This patch rearranges CVE-2024-5660 apply order in Cortex-A78_AE.
Signed-off-by: Arvind Ram Prakash <arvind.ramprakash@arm.com>
Change-Id: Idfb076b798a840847c00066bd062ee919369272f
This patch rearranges CVE-2024-5660 apply order in Cortex-A78.
Signed-off-by: Arvind Ram Prakash <arvind.ramprakash@arm.com>
Change-Id: If80a0f95f82dbf69100a2687b06db2373a9e9832
This patch rearranges CVE-2024-5660 apply order in Cortex-A77.
Signed-off-by: Arvind Ram Prakash <arvind.ramprakash@arm.com>
Change-Id: I41d76268ce2248bfd3600bbf6b89d16b6bdce8f0
Previously we have used enclosed the Errata ordering check
within the FEATURE_DETECTION flag as this flag is only
used for development purpose and it also enforces
ordering by causing a panic when the assert fails.
A simple warning message would suffice and hence this
patch removes the assert.
The erratum and cve ordering check is planned to be implemented
in static check at which point the warning will be taken out as well.
Signed-off-by: Arvind Ram Prakash <arvind.ramprakash@arm.com>
Change-Id: I0ffc40361985281163970ea5bc81ca0269b16442
When mcusys is off, rdist_ctx will save the rdist data of the last core.
In the case of the last core plug off, the data of other cores will be
inconsistent with the data in rdist_ctx.
Therefore, each core needs to use a dedicated context.
Signed-off-by: Runyang Chen <runyang.chen@mediatek.com>
Change-Id: Ic9501f4da219cf906c0e348982be3f550c3ba30b
Refactor `arm_sp_min_early_platform_setup` to accept generic
`u_register_r` values to support receiving firmware handoff boot
arguments in common code. This has the added benefit of simplifying the
interface into common early platform setup.
Change-Id: Idfc3d41f94f2bf3a3a0c7ca39f6b9b0013836e3a
Signed-off-by: Harrison Mutai <harrison.mutai@arm.com>
Commit fe488c3796 added an override to
force `CTX_INCLUDE_SVE_REGS` to 0 when `SPD == spmd` and
`SPMD_SPM_AT_SEL2 == 1`.
Since there is an architectural dependency between FP and SVE registers,
`CTX_INCLUDE_FPREGS` must also be overridden to 0 when
CTX_INCLUDE_SVE_REGS is 0.
Signed-off-by: Rakshit Goyal <rakshit.goyal@arm.com>
Change-Id: I1cd834241a2d5a5368ac532a348d8729a701bbcd
