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https://github.com/ARM-software/arm-trusted-firmware.git
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Merge changes from topic "ar/cvereorder" into integration
* changes: chore(cpus): rearrange the errata and cve order in Neoverse-N2 chore(cpus): rearrange cve in order in Cortex-X1 chore(cpus): fix cve order in Neoverse-V1 chore(cpus): fix cve order in Cortex-X2 chore(cpus): fix cve order in Cortex-A78C chore(cpus): fix cve order in Cortex-A78_AE chore(cpus): fix cve order in Cortex-A78 chore(cpus): fix cve order in Cortex-A77
This commit is contained in:
Bipin Ravi
TrustedFirmware Code Review
commit
4a871b56b4
8 changed files with 94 additions and 94 deletions
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@ -28,13 +28,6 @@ cpu_reset_prologue cortex_a77
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wa_cve_2022_23960_bhb_vector_table CORTEX_A77_BHB_LOOP_COUNT, cortex_a77
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#endif /* WORKAROUND_CVE_2022_23960 */
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/* Disable hardware page aggregation. Enables mitigation for `CVE-2024-5660` */
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workaround_reset_start cortex_a77, CVE(2024, 5660), WORKAROUND_CVE_2024_5660
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sysreg_bit_set CORTEX_A77_CPUECTLR_EL1, BIT(46)
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workaround_reset_end cortex_a77, CVE(2024, 5660)
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check_erratum_ls cortex_a77, CVE(2024, 5660), CPU_REV(1, 1)
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workaround_reset_start cortex_a77, ERRATUM(1508412), ERRATA_A77_1508412
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/* move cpu revision in again and compare against r0p0 */
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mov x0, x7
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@ -150,6 +143,13 @@ workaround_reset_end cortex_a77, CVE(2022, 23960)
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check_erratum_chosen cortex_a77, CVE(2022, 23960), WORKAROUND_CVE_2022_23960
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/* Disable hardware page aggregation. Enables mitigation for `CVE-2024-5660` */
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workaround_reset_start cortex_a77, CVE(2024, 5660), WORKAROUND_CVE_2024_5660
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sysreg_bit_set CORTEX_A77_CPUECTLR_EL1, BIT(46)
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workaround_reset_end cortex_a77, CVE(2024, 5660)
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check_erratum_ls cortex_a77, CVE(2024, 5660), CPU_REV(1, 1)
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/* -------------------------------------------------
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* The CPU Ops reset function for Cortex-A77. Must follow AAPCS.
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* -------------------------------------------------
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@ -26,13 +26,6 @@
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cpu_reset_prologue cortex_a78
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/* Disable hardware page aggregation.Enables mitigation for `CVE-2024-5660` */
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workaround_reset_start cortex_a78, CVE(2024, 5660), WORKAROUND_CVE_2024_5660
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sysreg_bit_set CORTEX_A78_CPUECTLR_EL1, BIT(46)
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workaround_reset_end cortex_a78, CVE(2024, 5660)
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check_erratum_ls cortex_a78, CVE(2024, 5660), CPU_REV(1, 2)
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workaround_reset_start cortex_a78, ERRATUM(1688305), ERRATA_A78_1688305
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sysreg_bit_set CORTEX_A78_ACTLR2_EL1, CORTEX_A78_ACTLR2_EL1_BIT_1
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workaround_reset_end cortex_a78, ERRATUM(1688305)
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@ -176,6 +169,13 @@ workaround_reset_end cortex_a78, CVE(2022, 23960)
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check_erratum_chosen cortex_a78, CVE(2022, 23960), WORKAROUND_CVE_2022_23960
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/* Disable hardware page aggregation.Enables mitigation for `CVE-2024-5660` */
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workaround_reset_start cortex_a78, CVE(2024, 5660), WORKAROUND_CVE_2024_5660
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sysreg_bit_set CORTEX_A78_CPUECTLR_EL1, BIT(46)
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workaround_reset_end cortex_a78, CVE(2024, 5660)
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check_erratum_ls cortex_a78, CVE(2024, 5660), CPU_REV(1, 2)
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cpu_reset_func_start cortex_a78
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#if ENABLE_FEAT_AMU
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/* Make sure accesses from EL0/EL1 and EL2 are not trapped to EL3 */
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@ -24,13 +24,6 @@
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cpu_reset_prologue cortex_a78_ae
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/* Disable hardware page aggregation. Enables mitigation for `CVE-2024-5660` */
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workaround_reset_start cortex_a78_ae, CVE(2024, 5660), WORKAROUND_CVE_2024_5660
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sysreg_bit_set CORTEX_A78_AE_CPUECTLR_EL1, BIT(46)
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workaround_reset_end cortex_a78_ae, CVE(2024, 5660)
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check_erratum_ls cortex_a78_ae, CVE(2024, 5660), CPU_REV(0, 3)
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workaround_reset_start cortex_a78_ae, ERRATUM(1941500), ERRATA_A78_AE_1941500
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sysreg_bit_set CORTEX_A78_AE_CPUECTLR_EL1, CORTEX_A78_AE_CPUECTLR_EL1_BIT_8
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workaround_reset_end cortex_a78_ae, ERRATUM(1941500)
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@ -105,6 +98,13 @@ workaround_reset_end cortex_a78_ae, CVE(2022, 23960)
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check_erratum_chosen cortex_a78_ae, CVE(2022, 23960), WORKAROUND_CVE_2022_23960
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/* Disable hardware page aggregation. Enables mitigation for `CVE-2024-5660` */
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workaround_reset_start cortex_a78_ae, CVE(2024, 5660), WORKAROUND_CVE_2024_5660
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sysreg_bit_set CORTEX_A78_AE_CPUECTLR_EL1, BIT(46)
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workaround_reset_end cortex_a78_ae, CVE(2024, 5660)
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check_erratum_ls cortex_a78_ae, CVE(2024, 5660), CPU_REV(0, 3)
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cpu_reset_func_start cortex_a78_ae
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#if ENABLE_FEAT_AMU
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/* Make sure accesses from EL0/EL1 and EL2 are not trapped to EL3 */
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@ -23,13 +23,6 @@
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cpu_reset_prologue cortex_a78c
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/* Disable hardware page aggregation. Enables mitigation for `CVE-2024-5660` */
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workaround_reset_start cortex_a78c, CVE(2024, 5660), WORKAROUND_CVE_2024_5660
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sysreg_bit_set CORTEX_A78C_CPUECTLR_EL1, BIT(46)
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workaround_reset_end cortex_a78c, CVE(2024, 5660)
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check_erratum_ls cortex_a78c, CVE(2024, 5660), CPU_REV(0, 2)
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workaround_reset_start cortex_a78c, ERRATUM(1827430), ERRATA_A78C_1827430
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/* Disable allocation of splintered pages in the L2 TLB */
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sysreg_bit_set CORTEX_A78C_CPUECTLR_EL1, CORTEX_A78C_CPUECTLR_EL1_MM_ASP_EN
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@ -127,6 +120,13 @@ workaround_reset_start cortex_a78c, CVE(2022, 23960), WORKAROUND_CVE_2022_23960
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#endif /* IMAGE_BL31 */
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workaround_reset_end cortex_a78c, CVE(2022, 23960)
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/* Disable hardware page aggregation. Enables mitigation for `CVE-2024-5660` */
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workaround_reset_start cortex_a78c, CVE(2024, 5660), WORKAROUND_CVE_2024_5660
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sysreg_bit_set CORTEX_A78C_CPUECTLR_EL1, BIT(46)
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workaround_reset_end cortex_a78c, CVE(2024, 5660)
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check_erratum_ls cortex_a78c, CVE(2024, 5660), CPU_REV(0, 2)
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cpu_reset_func_start cortex_a78c
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cpu_reset_func_end cortex_a78c
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@ -25,13 +25,6 @@
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cpu_reset_prologue cortex_x1
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/* Disable hardware page aggregation. Enables mitigation for `CVE-2024-5660` */
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workaround_reset_start cortex_x1, CVE(2024, 5660), WORKAROUND_CVE_2024_5660
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sysreg_bit_set CORTEX_X1_CPUECTLR_EL1, BIT(46)
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workaround_reset_end cortex_x1, CVE(2024, 5660)
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check_erratum_ls cortex_x1, CVE(2024, 5660), CPU_REV(1, 2)
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workaround_reset_start cortex_x1, ERRATUM(1688305), ERRATA_X1_1688305
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sysreg_bit_set CORTEX_X1_ACTLR2_EL1, BIT(1)
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workaround_reset_end cortex_x1, ERRATUM(1688305)
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@ -62,6 +55,13 @@ workaround_reset_start cortex_x1, CVE(2022, 23960), WORKAROUND_CVE_2022_23960
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#endif /* IMAGE_BL31 */
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workaround_reset_end cortex_x1, CVE(2022, 23960)
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/* Disable hardware page aggregation. Enables mitigation for `CVE-2024-5660` */
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workaround_reset_start cortex_x1, CVE(2024, 5660), WORKAROUND_CVE_2024_5660
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sysreg_bit_set CORTEX_X1_CPUECTLR_EL1, BIT(46)
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workaround_reset_end cortex_x1, CVE(2024, 5660)
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check_erratum_ls cortex_x1, CVE(2024, 5660), CPU_REV(1, 2)
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cpu_reset_func_start cortex_x1
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cpu_reset_func_end cortex_x1
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@ -25,23 +25,12 @@
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.global check_erratum_cortex_x2_3701772
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add_erratum_entry cortex_x2, ERRATUM(3701772), ERRATA_X2_3701772
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check_erratum_ls cortex_x2, ERRATUM(3701772), CPU_REV(2, 1)
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#if WORKAROUND_CVE_2022_23960
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wa_cve_2022_23960_bhb_vector_table CORTEX_X2_BHB_LOOP_COUNT, cortex_x2
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#endif /* WORKAROUND_CVE_2022_23960 */
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cpu_reset_prologue cortex_x2
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/* Disable hardware page aggregation. Enables mitigation for `CVE-2024-5660` */
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workaround_reset_start cortex_x2, CVE(2024, 5660), WORKAROUND_CVE_2024_5660
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sysreg_bit_set CORTEX_X2_CPUECTLR_EL1, BIT(46)
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workaround_reset_end cortex_x2, CVE(2024, 5660)
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check_erratum_ls cortex_x2, CVE(2024, 5660), CPU_REV(2, 1)
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workaround_reset_start cortex_x2, ERRATUM(2002765), ERRATA_X2_2002765
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ldr x0, =0x6
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msr S3_6_C15_C8_0, x0 /* CPUPSELR_EL3 */
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@ -127,6 +116,15 @@ workaround_reset_end cortex_x2, ERRATUM(2282622)
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check_erratum_ls cortex_x2, ERRATUM(2282622), CPU_REV(2, 1)
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workaround_reset_start cortex_x2, ERRATUM(2313941), ERRATA_DSU_2313941
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errata_dsu_2313941_wa_impl
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workaround_reset_end cortex_x2, ERRATUM(2313941)
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check_erratum_custom_start cortex_x2, ERRATUM(2313941)
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check_errata_dsu_2313941_impl
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ret
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check_erratum_custom_end cortex_x2, ERRATUM(2313941)
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workaround_reset_start cortex_x2, ERRATUM(2371105), ERRATA_X2_2371105
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/* Set bit 40 in CPUACTLR2_EL1 */
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sysreg_bit_set CORTEX_X2_CPUACTLR2_EL1, CORTEX_X2_CPUACTLR2_EL1_BIT_40
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@ -155,6 +153,10 @@ workaround_reset_end cortex_x2, ERRATUM(2778471)
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check_erratum_ls cortex_x2, ERRATUM(2778471), CPU_REV(2, 1)
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add_erratum_entry cortex_x2, ERRATUM(3701772), ERRATA_X2_3701772
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check_erratum_ls cortex_x2, ERRATUM(3701772), CPU_REV(2, 1)
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workaround_reset_start cortex_x2, CVE(2022, 23960), WORKAROUND_CVE_2022_23960
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#if IMAGE_BL31
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/*
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@ -167,14 +169,12 @@ workaround_reset_end cortex_x2, CVE(2022, 23960)
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check_erratum_chosen cortex_x2, CVE(2022, 23960), WORKAROUND_CVE_2022_23960
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workaround_reset_start cortex_x2, ERRATUM(2313941), ERRATA_DSU_2313941
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errata_dsu_2313941_wa_impl
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workaround_reset_end cortex_x2, ERRATUM(2313941)
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/* Disable hardware page aggregation. Enables mitigation for `CVE-2024-5660` */
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workaround_reset_start cortex_x2, CVE(2024, 5660), WORKAROUND_CVE_2024_5660
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sysreg_bit_set CORTEX_X2_CPUECTLR_EL1, BIT(46)
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workaround_reset_end cortex_x2, CVE(2024, 5660)
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check_erratum_custom_start cortex_x2, ERRATUM(2313941)
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check_errata_dsu_2313941_impl
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ret
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check_erratum_custom_end cortex_x2, ERRATUM(2313941)
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check_erratum_ls cortex_x2, CVE(2024, 5660), CPU_REV(2, 1)
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/* ----------------------------------------------------
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* HW will do the cache maintenance while powering down
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@ -23,34 +23,12 @@
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.global check_erratum_neoverse_n2_3701773
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add_erratum_entry neoverse_n2, ERRATUM(3701773), ERRATA_N2_3701773
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check_erratum_ls neoverse_n2, ERRATUM(3701773), CPU_REV(0, 3)
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#if WORKAROUND_CVE_2022_23960
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wa_cve_2022_23960_bhb_vector_table NEOVERSE_N2_BHB_LOOP_COUNT, neoverse_n2
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#endif /* WORKAROUND_CVE_2022_23960 */
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cpu_reset_prologue neoverse_n2
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workaround_reset_start neoverse_n2, ERRATUM(2313941), ERRATA_DSU_2313941
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errata_dsu_2313941_wa_impl
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workaround_reset_end neoverse_n2, ERRATUM(2313941)
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check_erratum_custom_start neoverse_n2, ERRATUM(2313941)
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branch_if_scu_not_present 2f /* label 1 is used in the macro */
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check_errata_dsu_2313941_impl
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2:
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ret
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check_erratum_custom_end neoverse_n2, ERRATUM(2313941)
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/* Disable hardware page aggregation. Enables mitigation for `CVE-2024-5660` */
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workaround_reset_start neoverse_n2, CVE(2024, 5660), WORKAROUND_CVE_2024_5660
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sysreg_bit_set NEOVERSE_N2_CPUECTLR_EL1, BIT(46)
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workaround_reset_end neoverse_n2, CVE(2024, 5660)
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check_erratum_ls neoverse_n2, CVE(2024, 5660), CPU_REV(0, 3)
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workaround_reset_start neoverse_n2, ERRATUM(2002655), ERRATA_N2_2002655
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/* Apply instruction patching sequence */
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ldr x0,=0x6
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@ -73,18 +51,6 @@ workaround_reset_end neoverse_n2, ERRATUM(2002655)
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check_erratum_ls neoverse_n2, ERRATUM(2002655), CPU_REV(0, 0)
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workaround_reset_start neoverse_n2, ERRATUM(2025414), ERRATA_N2_2025414
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sysreg_bit_set NEOVERSE_N2_CPUECTLR_EL1, NEOVERSE_N2_CPUECTLR_EL1_PFSTIDIS_BIT
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workaround_reset_end neoverse_n2, ERRATUM(2025414)
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check_erratum_ls neoverse_n2, ERRATUM(2025414), CPU_REV(0, 0)
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workaround_reset_start neoverse_n2, ERRATUM(2067956), ERRATA_N2_2067956
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sysreg_bit_set NEOVERSE_N2_CPUACTLR_EL1, NEOVERSE_N2_CPUACTLR_EL1_BIT_46
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workaround_reset_end neoverse_n2, ERRATUM(2067956)
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check_erratum_ls neoverse_n2, ERRATUM(2067956), CPU_REV(0, 0)
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workaround_runtime_start neoverse_n2, ERRATUM(2009478), ERRATA_N2_2009478
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/* Stash ERRSELR_EL1 in x2 */
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mrs x2, ERRSELR_EL1
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@ -101,6 +67,18 @@ workaround_runtime_end neoverse_n2, ERRATUM(2009478), NO_ISB
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check_erratum_ls neoverse_n2, ERRATUM(2009478), CPU_REV(0, 0)
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workaround_reset_start neoverse_n2, ERRATUM(2025414), ERRATA_N2_2025414
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sysreg_bit_set NEOVERSE_N2_CPUECTLR_EL1, NEOVERSE_N2_CPUECTLR_EL1_PFSTIDIS_BIT
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workaround_reset_end neoverse_n2, ERRATUM(2025414)
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check_erratum_ls neoverse_n2, ERRATUM(2025414), CPU_REV(0, 0)
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workaround_reset_start neoverse_n2, ERRATUM(2067956), ERRATA_N2_2067956
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sysreg_bit_set NEOVERSE_N2_CPUACTLR_EL1, NEOVERSE_N2_CPUACTLR_EL1_BIT_46
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workaround_reset_end neoverse_n2, ERRATUM(2067956)
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check_erratum_ls neoverse_n2, ERRATUM(2067956), CPU_REV(0, 0)
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workaround_reset_start neoverse_n2, ERRATUM(2138953), ERRATA_N2_2138953
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/* Apply instruction patching sequence */
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mrs x1, NEOVERSE_N2_CPUECTLR2_EL1
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@ -175,6 +153,17 @@ workaround_reset_end neoverse_n2, ERRATUM(2280757)
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check_erratum_ls neoverse_n2, ERRATUM(2280757), CPU_REV(0, 0)
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workaround_reset_start neoverse_n2, ERRATUM(2313941), ERRATA_DSU_2313941
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errata_dsu_2313941_wa_impl
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workaround_reset_end neoverse_n2, ERRATUM(2313941)
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check_erratum_custom_start neoverse_n2, ERRATUM(2313941)
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branch_if_scu_not_present 2f /* label 1 is used in the macro */
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check_errata_dsu_2313941_impl
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2:
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ret
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check_erratum_custom_end neoverse_n2, ERRATUM(2313941)
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.global erratum_neoverse_n2_2326639_wa
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workaround_runtime_start neoverse_n2, ERRATUM(2326639), ERRATA_N2_2326639
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/* Set/unset bit 36 in ACTLR2_EL1. The first call will set it, applying
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@ -240,6 +229,10 @@ workaround_reset_end neoverse_n2, ERRATUM(2779511)
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check_erratum_ls neoverse_n2, ERRATUM(2779511), CPU_REV(0, 2)
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add_erratum_entry neoverse_n2, ERRATUM(3701773), ERRATA_N2_3701773
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check_erratum_ls neoverse_n2, ERRATUM(3701773), CPU_REV(0, 3)
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workaround_reset_start neoverse_n2, CVE(2022,23960), WORKAROUND_CVE_2022_23960
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#if IMAGE_BL31
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/*
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||||
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@ -252,6 +245,13 @@ workaround_reset_end neoverse_n2, CVE(2022,23960)
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|
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check_erratum_chosen neoverse_n2, CVE(2022, 23960), WORKAROUND_CVE_2022_23960
|
||||
|
||||
/* Disable hardware page aggregation. Enables mitigation for `CVE-2024-5660` */
|
||||
workaround_reset_start neoverse_n2, CVE(2024, 5660), WORKAROUND_CVE_2024_5660
|
||||
sysreg_bit_set NEOVERSE_N2_CPUECTLR_EL1, BIT(46)
|
||||
workaround_reset_end neoverse_n2, CVE(2024, 5660)
|
||||
|
||||
check_erratum_ls neoverse_n2, CVE(2024, 5660), CPU_REV(0, 3)
|
||||
|
||||
/* -------------------------------------------
|
||||
* The CPU Ops reset function for Neoverse N2.
|
||||
* -------------------------------------------
|
||||
|
|
|
|||
|
|
@ -28,13 +28,6 @@ cpu_reset_prologue neoverse_v1
|
|||
wa_cve_2022_23960_bhb_vector_table NEOVERSE_V1_BHB_LOOP_COUNT, neoverse_v1
|
||||
#endif /* WORKAROUND_CVE_2022_23960 */
|
||||
|
||||
/* Disable hardware page aggregation. Enables mitigation for `CVE-2024-5660` */
|
||||
workaround_reset_start neoverse_v1, CVE(2024, 5660), WORKAROUND_CVE_2024_5660
|
||||
sysreg_bit_set NEOVERSE_V1_CPUECTLR_EL1, BIT(46)
|
||||
workaround_reset_end neoverse_v1, CVE(2024, 5660)
|
||||
|
||||
check_erratum_ls neoverse_v1, CVE(2024, 5660), CPU_REV(1, 2)
|
||||
|
||||
workaround_reset_start neoverse_v1, ERRATUM(1618635), ERRATA_V1_1618635
|
||||
/* Inserts a DMB SY before and after MRS PAR_EL1 */
|
||||
ldr x0, =0x0
|
||||
|
|
@ -252,6 +245,13 @@ workaround_reset_end neoverse_v1, CVE(2022,23960)
|
|||
|
||||
check_erratum_chosen neoverse_v1, CVE(2022, 23960), WORKAROUND_CVE_2022_23960
|
||||
|
||||
/* Disable hardware page aggregation. Enables mitigation for `CVE-2024-5660` */
|
||||
workaround_reset_start neoverse_v1, CVE(2024, 5660), WORKAROUND_CVE_2024_5660
|
||||
sysreg_bit_set NEOVERSE_V1_CPUECTLR_EL1, BIT(46)
|
||||
workaround_reset_end neoverse_v1, CVE(2024, 5660)
|
||||
|
||||
check_erratum_ls neoverse_v1, CVE(2024, 5660), CPU_REV(1, 2)
|
||||
|
||||
/* ---------------------------------------------
|
||||
* HW will do the cache maintenance while powering down
|
||||
* ---------------------------------------------
|
||||
|
|
|
|||
Loading…
Add table
Reference in a new issue