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chore(cpus): rearrange the errata and cve order in Neoverse-N2

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Patch sorts the errata IDs in ascending order and the
CVE's in ascending order based on the year and index
for CPU Neoverse N2.

Change-Id: Ieb4a8ab0030ea4e83efdef86a0ff1e2990b3e0dd
Signed-off-by: Sona Mathew <sonarebecca.mathew@arm.com>
This commit is contained in:
Sona Mathew 2025-03-19 15:20:15 -05:00 • committed by Arvind Ram Prakash
parent e83cccfec4
commit 216d437c0d
1 changed files with 34 additions and 34 deletions
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68
lib/cpus/aarch64/neoverse_n2.S
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@ -23,34 +23,12 @@
.global check_erratum_neoverse_n2_3701773
add_erratum_entry neoverse_n2, ERRATUM(3701773), ERRATA_N2_3701773
check_erratum_ls neoverse_n2, ERRATUM(3701773), CPU_REV(0, 3)
#if WORKAROUND_CVE_2022_23960
wa_cve_2022_23960_bhb_vector_table NEOVERSE_N2_BHB_LOOP_COUNT, neoverse_n2
#endif /* WORKAROUND_CVE_2022_23960 */
cpu_reset_prologue neoverse_n2
workaround_reset_start neoverse_n2, ERRATUM(2313941), ERRATA_DSU_2313941
errata_dsu_2313941_wa_impl
workaround_reset_end neoverse_n2, ERRATUM(2313941)
check_erratum_custom_start neoverse_n2, ERRATUM(2313941)
branch_if_scu_not_present 2f /* label 1 is used in the macro */
check_errata_dsu_2313941_impl
2:
ret
check_erratum_custom_end neoverse_n2, ERRATUM(2313941)
/* Disable hardware page aggregation. Enables mitigation for `CVE-2024-5660` */
workaround_reset_start neoverse_n2, CVE(2024, 5660), WORKAROUND_CVE_2024_5660
sysreg_bit_set NEOVERSE_N2_CPUECTLR_EL1, BIT(46)
workaround_reset_end neoverse_n2, CVE(2024, 5660)
check_erratum_ls neoverse_n2, CVE(2024, 5660), CPU_REV(0, 3)
workaround_reset_start neoverse_n2, ERRATUM(2002655), ERRATA_N2_2002655
/* Apply instruction patching sequence */
ldr x0,=0x6
@ -73,18 +51,6 @@ workaround_reset_end neoverse_n2, ERRATUM(2002655)
check_erratum_ls neoverse_n2, ERRATUM(2002655), CPU_REV(0, 0)
workaround_reset_start neoverse_n2, ERRATUM(2025414), ERRATA_N2_2025414
sysreg_bit_set NEOVERSE_N2_CPUECTLR_EL1, NEOVERSE_N2_CPUECTLR_EL1_PFSTIDIS_BIT
workaround_reset_end neoverse_n2, ERRATUM(2025414)
check_erratum_ls neoverse_n2, ERRATUM(2025414), CPU_REV(0, 0)
workaround_reset_start neoverse_n2, ERRATUM(2067956), ERRATA_N2_2067956
sysreg_bit_set NEOVERSE_N2_CPUACTLR_EL1, NEOVERSE_N2_CPUACTLR_EL1_BIT_46
workaround_reset_end neoverse_n2, ERRATUM(2067956)
check_erratum_ls neoverse_n2, ERRATUM(2067956), CPU_REV(0, 0)
workaround_runtime_start neoverse_n2, ERRATUM(2009478), ERRATA_N2_2009478
/* Stash ERRSELR_EL1 in x2 */
mrs x2, ERRSELR_EL1
@ -101,6 +67,18 @@ workaround_runtime_end neoverse_n2, ERRATUM(2009478), NO_ISB
check_erratum_ls neoverse_n2, ERRATUM(2009478), CPU_REV(0, 0)
workaround_reset_start neoverse_n2, ERRATUM(2025414), ERRATA_N2_2025414
sysreg_bit_set NEOVERSE_N2_CPUECTLR_EL1, NEOVERSE_N2_CPUECTLR_EL1_PFSTIDIS_BIT
workaround_reset_end neoverse_n2, ERRATUM(2025414)
check_erratum_ls neoverse_n2, ERRATUM(2025414), CPU_REV(0, 0)
workaround_reset_start neoverse_n2, ERRATUM(2067956), ERRATA_N2_2067956
sysreg_bit_set NEOVERSE_N2_CPUACTLR_EL1, NEOVERSE_N2_CPUACTLR_EL1_BIT_46
workaround_reset_end neoverse_n2, ERRATUM(2067956)
check_erratum_ls neoverse_n2, ERRATUM(2067956), CPU_REV(0, 0)
workaround_reset_start neoverse_n2, ERRATUM(2138953), ERRATA_N2_2138953
/* Apply instruction patching sequence */
mrs x1, NEOVERSE_N2_CPUECTLR2_EL1
@ -175,6 +153,17 @@ workaround_reset_end neoverse_n2, ERRATUM(2280757)
check_erratum_ls neoverse_n2, ERRATUM(2280757), CPU_REV(0, 0)
workaround_reset_start neoverse_n2, ERRATUM(2313941), ERRATA_DSU_2313941
errata_dsu_2313941_wa_impl
workaround_reset_end neoverse_n2, ERRATUM(2313941)
check_erratum_custom_start neoverse_n2, ERRATUM(2313941)
branch_if_scu_not_present 2f /* label 1 is used in the macro */
check_errata_dsu_2313941_impl
2:
ret
check_erratum_custom_end neoverse_n2, ERRATUM(2313941)
.global erratum_neoverse_n2_2326639_wa
workaround_runtime_start neoverse_n2, ERRATUM(2326639), ERRATA_N2_2326639
/* Set/unset bit 36 in ACTLR2_EL1. The first call will set it, applying
@ -240,6 +229,10 @@ workaround_reset_end neoverse_n2, ERRATUM(2779511)
check_erratum_ls neoverse_n2, ERRATUM(2779511), CPU_REV(0, 2)
add_erratum_entry neoverse_n2, ERRATUM(3701773), ERRATA_N2_3701773
check_erratum_ls neoverse_n2, ERRATUM(3701773), CPU_REV(0, 3)
workaround_reset_start neoverse_n2, CVE(2022,23960), WORKAROUND_CVE_2022_23960
#if IMAGE_BL31
/*
@ -252,6 +245,13 @@ workaround_reset_end neoverse_n2, CVE(2022,23960)
check_erratum_chosen neoverse_n2, CVE(2022, 23960), WORKAROUND_CVE_2022_23960
/* Disable hardware page aggregation. Enables mitigation for `CVE-2024-5660` */
workaround_reset_start neoverse_n2, CVE(2024, 5660), WORKAROUND_CVE_2024_5660
sysreg_bit_set NEOVERSE_N2_CPUECTLR_EL1, BIT(46)
workaround_reset_end neoverse_n2, CVE(2024, 5660)
check_erratum_ls neoverse_n2, CVE(2024, 5660), CPU_REV(0, 3)
/* -------------------------------------------
* The CPU Ops reset function for Neoverse N2.
* -------------------------------------------