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chore(cpus): rearrange the errata and cve in order in Cortex-X4

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Patch sorts the errata IDs in ascending order and the
CVE's in ascending order based on the year and index
for CPU Cortex-X4.

Change-Id: Ic304c2f68e7d0b96bbb30760696b7bceabe1ae2d
Signed-off-by: Sona Mathew <sonarebecca.mathew@arm.com>
This commit is contained in:
Sona Mathew 2025-03-19 18:24:23 -05:00 • committed by Arvind Ram Prakash
parent 4cf62406ed
commit ede127e66c
1 changed files with 11 additions and 11 deletions
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22
lib/cpus/aarch64/cortex_x4.S
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@ -35,13 +35,6 @@ add_erratum_entry cortex_x4, ERRATUM(2726228), ERRATA_X4_2726228
check_erratum_ls cortex_x4, ERRATUM(2726228), CPU_REV(0, 1)
/* Disable hardware page aggregation. Enables mitigation for `CVE-2024-5660` */
workaround_reset_start cortex_x4, CVE(2024, 5660), WORKAROUND_CVE_2024_5660
sysreg_bit_set CORTEX_X4_CPUECTLR_EL1, BIT(46)
workaround_reset_end cortex_x4, CVE(2024, 5660)
check_erratum_ls cortex_x4, CVE(2024, 5660), CPU_REV(0, 2)
workaround_runtime_start cortex_x4, ERRATUM(2740089), ERRATA_X4_2740089
/* dsb before isb of power down sequence */
dsb sy
@ -100,6 +93,10 @@ workaround_reset_end cortex_x4, ERRATUM(3076789)
check_erratum_ls cortex_x4, ERRATUM(3076789), CPU_REV(0, 1)
add_erratum_entry cortex_x4, ERRATUM(3701758), ERRATA_X4_3701758
check_erratum_ls cortex_x4, ERRATUM(3701758), CPU_REV(0, 3)
workaround_reset_start cortex_x4, CVE(2022, 23960), WORKAROUND_CVE_2022_23960
#if IMAGE_BL31
/*
@ -112,6 +109,13 @@ workaround_reset_end cortex_x4, CVE(2022, 23960)
check_erratum_chosen cortex_x4, CVE(2022, 23960), WORKAROUND_CVE_2022_23960
/* Disable hardware page aggregation. Enables mitigation for `CVE-2024-5660` */
workaround_reset_start cortex_x4, CVE(2024, 5660), WORKAROUND_CVE_2024_5660
sysreg_bit_set CORTEX_X4_CPUECTLR_EL1, BIT(46)
workaround_reset_end cortex_x4, CVE(2024, 5660)
check_erratum_ls cortex_x4, CVE(2024, 5660), CPU_REV(0, 2)
workaround_reset_start cortex_x4, CVE(2024, 7881), WORKAROUND_CVE_2024_7881
/* ---------------------------------
* Sets BIT41 of CPUACTLR6_EL1 which
@ -123,10 +127,6 @@ workaround_reset_end cortex_x4, CVE(2024, 7881)
check_erratum_chosen cortex_x4, CVE(2024, 7881), WORKAROUND_CVE_2024_7881
add_erratum_entry cortex_x4, ERRATUM(3701758), ERRATA_X4_3701758
check_erratum_ls cortex_x4, ERRATUM(3701758), CPU_REV(0, 3)
cpu_reset_func_start cortex_x4
/* Disable speculative loads */
msr SSBS, xzr