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Merge changes from topic "xlnx_fix_gen_datatype_cast" into integration

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* changes:
  fix(psci): add const qualifier
  fix(el3-runtime): add const qualifier
  fix(bl31): add const qualifier
  fix(console): typecast expressions to match data type
  fix(arm-drivers): typecast expressions to match data type
  fix(arm-drivers): align essential type categories
  fix(arm-drivers): typecast expression to match data type
This commit is contained in:
Govindraj Raja 2025-03-27 15:53:57 +01:00 • committed by TrustedFirmware Code Review
commit 2377542785
8 changed files with 22 additions and 19 deletions
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2
bl31/bl31_main.c
View file

@ -255,7 +255,7 @@ uint32_t bl31_get_next_image_type(void)
******************************************************************************/
void __init bl31_prepare_next_image_entry(void)
{
entry_point_info_t *next_image_info;
const entry_point_info_t *next_image_info;
uint32_t image_type;
#if CTX_INCLUDE_AARCH32_REGS

4
drivers/arm/cci/cci.c
View file

@ -143,7 +143,7 @@ void cci_enable_snoop_dvm_reqs(unsigned int master_id)
* rest of bits are write ignore
*/
mmio_write_32(cci_base +
SLAVE_IFACE_OFFSET(slave_if_id) + SNOOP_CTRL_REG,
SLAVE_IFACE_OFFSET((u_register_t)slave_if_id) + SNOOP_CTRL_REG,
DVM_EN_BIT | SNOOP_EN_BIT);
/*
@ -171,7 +171,7 @@ void cci_disable_snoop_dvm_reqs(unsigned int master_id)
* rest of bits are write ignore.
*/
mmio_write_32(cci_base +
SLAVE_IFACE_OFFSET(slave_if_id) + SNOOP_CTRL_REG,
SLAVE_IFACE_OFFSET((u_register_t)slave_if_id) + SNOOP_CTRL_REG,
~(DVM_EN_BIT | SNOOP_EN_BIT));
/*

17
drivers/arm/gic/v2/gicdv2_helpers.c
View file

@ -8,6 +8,7 @@
#include <drivers/arm/gic_common.h>
#include <lib/mmio.h>
#include <lib/utils_def.h>
#include "../common/gic_common_private.h"
@ -256,7 +257,7 @@ void gicd_set_igroupr(uintptr_t base, unsigned int id)
unsigned int bit_num = id & ((1U << IGROUPR_SHIFT) - 1U);
unsigned int reg_val = gicd_read_igroupr(base, id);
gicd_write_igroupr(base, id, reg_val | (1U << bit_num));
gicd_write_igroupr(base, id, reg_val | BIT_32(bit_num));
}
void gicd_clr_igroupr(uintptr_t base, unsigned int id)
@ -264,35 +265,35 @@ void gicd_clr_igroupr(uintptr_t base, unsigned int id)
unsigned int bit_num = id & ((1U << IGROUPR_SHIFT) - 1U);
unsigned int reg_val = gicd_read_igroupr(base, id);
gicd_write_igroupr(base, id, reg_val & ~(1U << bit_num));
gicd_write_igroupr(base, id, reg_val & ~BIT_32(bit_num));
}
void gicd_set_isenabler(uintptr_t base, unsigned int id)
{
unsigned int bit_num = id & ((1U << ISENABLER_SHIFT) - 1U);
gicd_write_isenabler(base, id, (1U << bit_num));
gicd_write_isenabler(base, id, BIT_32(bit_num));
}
void gicd_set_icenabler(uintptr_t base, unsigned int id)
{
unsigned int bit_num = id & ((1U << ICENABLER_SHIFT) - 1U);
gicd_write_icenabler(base, id, (1U << bit_num));
gicd_write_icenabler(base, id, BIT_32(bit_num));
}
void gicd_set_ispendr(uintptr_t base, unsigned int id)
{
unsigned int bit_num = id & ((1U << ISPENDR_SHIFT) - 1U);
gicd_write_ispendr(base, id, (1U << bit_num));
gicd_write_ispendr(base, id, BIT_32(bit_num));
}
void gicd_set_icpendr(uintptr_t base, unsigned int id)
{
unsigned int bit_num = id & ((1U << ICPENDR_SHIFT) - 1U);
gicd_write_icpendr(base, id, (1U << bit_num));
gicd_write_icpendr(base, id, BIT_32(bit_num));
}
unsigned int gicd_get_isactiver(uintptr_t base, unsigned int id)
@ -307,14 +308,14 @@ void gicd_set_isactiver(uintptr_t base, unsigned int id)
{
unsigned int bit_num = id & ((1U << ISACTIVER_SHIFT) - 1U);
gicd_write_isactiver(base, id, (1U << bit_num));
gicd_write_isactiver(base, id, BIT_32(bit_num));
}
void gicd_set_icactiver(uintptr_t base, unsigned int id)
{
unsigned int bit_num = id & ((1U << ICACTIVER_SHIFT) - 1U);
gicd_write_icactiver(base, id, (1U << bit_num));
gicd_write_icactiver(base, id, BIT_32(bit_num));
}
void gicd_set_ipriorityr(uintptr_t base, unsigned int id, unsigned int pri)

3
drivers/arm/gic/v2/gicv2_helpers.c
View file

@ -11,6 +11,7 @@
#include <common/interrupt_props.h>
#include <drivers/arm/gic_common.h>
#include <drivers/arm/gicv2.h>
#include <lib/utils_def.h>
#include "../common/gic_common_private.h"
#include "gicv2_private.h"
@ -203,7 +204,7 @@ void gicv2_secure_ppi_sgi_setup_props(uintptr_t gicd_base,
}
/* We have an SGI or a PPI. They are Group0 at reset */
sec_ppi_sgi_mask |= (1u << prop_desc->intr_num);
sec_ppi_sgi_mask |= BIT_32((uint32_t)prop_desc->intr_num);
/* Set the priority of this interrupt */
gicd_set_ipriorityr(gicd_base, prop_desc->intr_num,

4
drivers/console/multi_console.c
View file

@ -79,8 +79,8 @@ static int do_putc(int c, console_t *console)
{
int ret;
if ((c == '\n') &&
((console->flags & CONSOLE_FLAG_TRANSLATE_CRLF) != 0)) {
if ((c == (int)'\n') &&
((console->flags & CONSOLE_FLAG_TRANSLATE_CRLF) != 0U)) {
ret = console->putc('\r', console);
if (ret < 0)
return ret;

2
include/drivers/console.h
View file

@ -27,7 +27,7 @@
#define CONSOLE_FLAG_RUNTIME (U(1) << 1)
#define CONSOLE_FLAG_CRASH (U(1) << 2)
/* Bits 3 to 7 reserved for additional scopes in future expansion. */
#define CONSOLE_FLAG_SCOPE_MASK ((U(1) << 8) - 1)
#define CONSOLE_FLAG_SCOPE_MASK GENMASK(7, 0)
/* Bits 8 to 31 for non-scope use. */
#define CONSOLE_FLAG_TRANSLATE_CRLF (U(1) << 8)

4
lib/el3_runtime/aarch64/context_mgmt.c
View file

@ -2071,8 +2071,8 @@ void cm_write_scr_el3_bit(uint32_t security_state,
******************************************************************************/
u_register_t cm_get_scr_el3(uint32_t security_state)
{
cpu_context_t *ctx;
el3_state_t *state;
const cpu_context_t *ctx;
const el3_state_t *state;
ctx = cm_get_context(security_state);
assert(ctx != NULL);

5
lib/psci/psci_common.c
View file

@ -546,7 +546,7 @@ void psci_do_state_coordination(unsigned int cpu_idx, unsigned int end_pwrlvl,
unsigned int lvl, parent_idx;
unsigned int start_idx;
unsigned int ncpus;
plat_local_state_t target_state, *req_states;
plat_local_state_t target_state;
assert(end_pwrlvl <= PLAT_MAX_PWR_LVL);
parent_idx = psci_cpu_pd_nodes[cpu_idx].parent_node;
@ -561,7 +561,8 @@ void psci_do_state_coordination(unsigned int cpu_idx, unsigned int end_pwrlvl,
/* Get the requested power states for this power level */
start_idx = psci_non_cpu_pd_nodes[parent_idx].cpu_start_idx;
req_states = psci_get_req_local_pwr_states(lvl, start_idx);
plat_local_state_t const *req_states = psci_get_req_local_pwr_states(lvl,
start_idx);
/*
* Let the platform coordinate amongst the requested states at