diff --git a/bl31/bl31_main.c b/bl31/bl31_main.c
index db0ea6cb1..0cd0c7958 100644
--- a/bl31/bl31_main.c
+++ b/bl31/bl31_main.c
@@ -255,7 +255,7 @@ uint32_t bl31_get_next_image_type(void)
  ******************************************************************************/
 void __init bl31_prepare_next_image_entry(void)
 {
-	entry_point_info_t *next_image_info;
+	const entry_point_info_t *next_image_info;
 	uint32_t image_type;
 
 #if CTX_INCLUDE_AARCH32_REGS
diff --git a/drivers/arm/cci/cci.c b/drivers/arm/cci/cci.c
index 40d2efdeb..ae2b9bb04 100644
--- a/drivers/arm/cci/cci.c
+++ b/drivers/arm/cci/cci.c
@@ -143,7 +143,7 @@ void cci_enable_snoop_dvm_reqs(unsigned int master_id)
 	 * rest of bits are write ignore
 	 */
 	mmio_write_32(cci_base +
-		      SLAVE_IFACE_OFFSET(slave_if_id) + SNOOP_CTRL_REG,
+		      SLAVE_IFACE_OFFSET((u_register_t)slave_if_id) + SNOOP_CTRL_REG,
 		      DVM_EN_BIT | SNOOP_EN_BIT);
 
 	/*
@@ -171,7 +171,7 @@ void cci_disable_snoop_dvm_reqs(unsigned int master_id)
 	 * rest of bits are write ignore.
 	 */
 	mmio_write_32(cci_base +
-		      SLAVE_IFACE_OFFSET(slave_if_id) + SNOOP_CTRL_REG,
+		      SLAVE_IFACE_OFFSET((u_register_t)slave_if_id) + SNOOP_CTRL_REG,
 		      ~(DVM_EN_BIT | SNOOP_EN_BIT));
 
 	/*
diff --git a/drivers/arm/gic/v2/gicdv2_helpers.c b/drivers/arm/gic/v2/gicdv2_helpers.c
index db9ba87c4..2f3f7f8dc 100644
--- a/drivers/arm/gic/v2/gicdv2_helpers.c
+++ b/drivers/arm/gic/v2/gicdv2_helpers.c
@@ -8,6 +8,7 @@
 
 #include <drivers/arm/gic_common.h>
 #include <lib/mmio.h>
+#include <lib/utils_def.h>
 
 #include "../common/gic_common_private.h"
 
@@ -256,7 +257,7 @@ void gicd_set_igroupr(uintptr_t base, unsigned int id)
 	unsigned int bit_num = id & ((1U << IGROUPR_SHIFT) - 1U);
 	unsigned int reg_val = gicd_read_igroupr(base, id);
 
-	gicd_write_igroupr(base, id, reg_val | (1U << bit_num));
+	gicd_write_igroupr(base, id, reg_val | BIT_32(bit_num));
 }
 
 void gicd_clr_igroupr(uintptr_t base, unsigned int id)
@@ -264,35 +265,35 @@ void gicd_clr_igroupr(uintptr_t base, unsigned int id)
 	unsigned int bit_num = id & ((1U << IGROUPR_SHIFT) - 1U);
 	unsigned int reg_val = gicd_read_igroupr(base, id);
 
-	gicd_write_igroupr(base, id, reg_val & ~(1U << bit_num));
+	gicd_write_igroupr(base, id, reg_val & ~BIT_32(bit_num));
 }
 
 void gicd_set_isenabler(uintptr_t base, unsigned int id)
 {
 	unsigned int bit_num = id & ((1U << ISENABLER_SHIFT) - 1U);
 
-	gicd_write_isenabler(base, id, (1U << bit_num));
+	gicd_write_isenabler(base, id, BIT_32(bit_num));
 }
 
 void gicd_set_icenabler(uintptr_t base, unsigned int id)
 {
 	unsigned int bit_num = id & ((1U << ICENABLER_SHIFT) - 1U);
 
-	gicd_write_icenabler(base, id, (1U << bit_num));
+	gicd_write_icenabler(base, id, BIT_32(bit_num));
 }
 
 void gicd_set_ispendr(uintptr_t base, unsigned int id)
 {
 	unsigned int bit_num = id & ((1U << ISPENDR_SHIFT) - 1U);
 
-	gicd_write_ispendr(base, id, (1U << bit_num));
+	gicd_write_ispendr(base, id, BIT_32(bit_num));
 }
 
 void gicd_set_icpendr(uintptr_t base, unsigned int id)
 {
 	unsigned int bit_num = id & ((1U << ICPENDR_SHIFT) - 1U);
 
-	gicd_write_icpendr(base, id, (1U << bit_num));
+	gicd_write_icpendr(base, id, BIT_32(bit_num));
 }
 
 unsigned int gicd_get_isactiver(uintptr_t base, unsigned int id)
@@ -307,14 +308,14 @@ void gicd_set_isactiver(uintptr_t base, unsigned int id)
 {
 	unsigned int bit_num = id & ((1U << ISACTIVER_SHIFT) - 1U);
 
-	gicd_write_isactiver(base, id, (1U << bit_num));
+	gicd_write_isactiver(base, id, BIT_32(bit_num));
 }
 
 void gicd_set_icactiver(uintptr_t base, unsigned int id)
 {
 	unsigned int bit_num = id & ((1U << ICACTIVER_SHIFT) - 1U);
 
-	gicd_write_icactiver(base, id, (1U << bit_num));
+	gicd_write_icactiver(base, id, BIT_32(bit_num));
 }
 
 void gicd_set_ipriorityr(uintptr_t base, unsigned int id, unsigned int pri)
diff --git a/drivers/arm/gic/v2/gicv2_helpers.c b/drivers/arm/gic/v2/gicv2_helpers.c
index a9ae0b53a..34154996b 100644
--- a/drivers/arm/gic/v2/gicv2_helpers.c
+++ b/drivers/arm/gic/v2/gicv2_helpers.c
@@ -11,6 +11,7 @@
 #include <common/interrupt_props.h>
 #include <drivers/arm/gic_common.h>
 #include <drivers/arm/gicv2.h>
+#include <lib/utils_def.h>
 
 #include "../common/gic_common_private.h"
 #include "gicv2_private.h"
@@ -203,7 +204,7 @@ void gicv2_secure_ppi_sgi_setup_props(uintptr_t gicd_base,
 		}
 
 		/* We have an SGI or a PPI. They are Group0 at reset */
-		sec_ppi_sgi_mask |= (1u << prop_desc->intr_num);
+		sec_ppi_sgi_mask |= BIT_32((uint32_t)prop_desc->intr_num);
 
 		/* Set the priority of this interrupt */
 		gicd_set_ipriorityr(gicd_base, prop_desc->intr_num,
diff --git a/drivers/console/multi_console.c b/drivers/console/multi_console.c
index 5ecbaed1d..59a4a868b 100644
--- a/drivers/console/multi_console.c
+++ b/drivers/console/multi_console.c
@@ -79,8 +79,8 @@ static int do_putc(int c, console_t *console)
 {
 	int ret;
 
-	if ((c == '\n') &&
-	    ((console->flags & CONSOLE_FLAG_TRANSLATE_CRLF) != 0)) {
+	if ((c == (int)'\n') &&
+	    ((console->flags & CONSOLE_FLAG_TRANSLATE_CRLF) != 0U)) {
 		ret = console->putc('\r', console);
 		if (ret < 0)
 			return ret;
diff --git a/include/drivers/console.h b/include/drivers/console.h
index fa4eb9462..0de2c99b7 100644
--- a/include/drivers/console.h
+++ b/include/drivers/console.h
@@ -27,7 +27,7 @@
 #define CONSOLE_FLAG_RUNTIME		(U(1) << 1)
 #define CONSOLE_FLAG_CRASH		(U(1) << 2)
 /* Bits 3 to 7 reserved for additional scopes in future expansion. */
-#define CONSOLE_FLAG_SCOPE_MASK		((U(1) << 8) - 1)
+#define CONSOLE_FLAG_SCOPE_MASK		GENMASK(7, 0)
 /* Bits 8 to 31 for non-scope use. */
 #define CONSOLE_FLAG_TRANSLATE_CRLF	(U(1) << 8)
 
diff --git a/lib/el3_runtime/aarch64/context_mgmt.c b/lib/el3_runtime/aarch64/context_mgmt.c
index f4fec42b9..021d5385f 100644
--- a/lib/el3_runtime/aarch64/context_mgmt.c
+++ b/lib/el3_runtime/aarch64/context_mgmt.c
@@ -2071,8 +2071,8 @@ void cm_write_scr_el3_bit(uint32_t security_state,
  ******************************************************************************/
 u_register_t cm_get_scr_el3(uint32_t security_state)
 {
-	cpu_context_t *ctx;
-	el3_state_t *state;
+	const cpu_context_t *ctx;
+	const el3_state_t *state;
 
 	ctx = cm_get_context(security_state);
 	assert(ctx != NULL);
diff --git a/lib/psci/psci_common.c b/lib/psci/psci_common.c
index 234a19509..2d3335031 100644
--- a/lib/psci/psci_common.c
+++ b/lib/psci/psci_common.c
@@ -546,7 +546,7 @@ void psci_do_state_coordination(unsigned int cpu_idx, unsigned int end_pwrlvl,
 	unsigned int lvl, parent_idx;
 	unsigned int start_idx;
 	unsigned int ncpus;
-	plat_local_state_t target_state, *req_states;
+	plat_local_state_t target_state;
 
 	assert(end_pwrlvl <= PLAT_MAX_PWR_LVL);
 	parent_idx = psci_cpu_pd_nodes[cpu_idx].parent_node;
@@ -561,7 +561,8 @@ void psci_do_state_coordination(unsigned int cpu_idx, unsigned int end_pwrlvl,
 
 		/* Get the requested power states for this power level */
 		start_idx = psci_non_cpu_pd_nodes[parent_idx].cpu_start_idx;
-		req_states = psci_get_req_local_pwr_states(lvl, start_idx);
+		plat_local_state_t const *req_states = psci_get_req_local_pwr_states(lvl,
+										start_idx);
 
 		/*
 		 * Let the platform coordinate amongst the requested states at