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chore(cpus): fix cve order in Cortex-X2

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This patch rearranges CVE-2024-5660, erratum 2313941
and 3701772 apply order in Cortex-X2.

Signed-off-by: Arvind Ram Prakash <arvind.ramprakash@arm.com>
Change-Id: Ie74d7232a14f3cdd14c4d0ffb1ee91b537c491ea
This commit is contained in:
Arvind Ram Prakash 2025-03-19 15:35:47 -05:00
parent 97b1023b46
commit eb9220b2d1
1 changed files with 18 additions and 18 deletions

36
lib/cpus/aarch64/cortex_x2.S
View file

@ -25,23 +25,12 @@
.global check_erratum_cortex_x2_3701772
add_erratum_entry cortex_x2, ERRATUM(3701772), ERRATA_X2_3701772
check_erratum_ls cortex_x2, ERRATUM(3701772), CPU_REV(2, 1)
#if WORKAROUND_CVE_2022_23960
wa_cve_2022_23960_bhb_vector_table CORTEX_X2_BHB_LOOP_COUNT, cortex_x2
#endif /* WORKAROUND_CVE_2022_23960 */
cpu_reset_prologue cortex_x2
/* Disable hardware page aggregation. Enables mitigation for `CVE-2024-5660` */
workaround_reset_start cortex_x2, CVE(2024, 5660), WORKAROUND_CVE_2024_5660
sysreg_bit_set CORTEX_X2_CPUECTLR_EL1, BIT(46)
workaround_reset_end cortex_x2, CVE(2024, 5660)
check_erratum_ls cortex_x2, CVE(2024, 5660), CPU_REV(2, 1)
workaround_reset_start cortex_x2, ERRATUM(2002765), ERRATA_X2_2002765
ldr x0, =0x6
msr S3_6_C15_C8_0, x0 /* CPUPSELR_EL3 */
@ -127,6 +116,15 @@ workaround_reset_end cortex_x2, ERRATUM(2282622)
check_erratum_ls cortex_x2, ERRATUM(2282622), CPU_REV(2, 1)
workaround_reset_start cortex_x2, ERRATUM(2313941), ERRATA_DSU_2313941
errata_dsu_2313941_wa_impl
workaround_reset_end cortex_x2, ERRATUM(2313941)
check_erratum_custom_start cortex_x2, ERRATUM(2313941)
check_errata_dsu_2313941_impl
ret
check_erratum_custom_end cortex_x2, ERRATUM(2313941)
workaround_reset_start cortex_x2, ERRATUM(2371105), ERRATA_X2_2371105
/* Set bit 40 in CPUACTLR2_EL1 */
sysreg_bit_set CORTEX_X2_CPUACTLR2_EL1, CORTEX_X2_CPUACTLR2_EL1_BIT_40
@ -155,6 +153,10 @@ workaround_reset_end cortex_x2, ERRATUM(2778471)
check_erratum_ls cortex_x2, ERRATUM(2778471), CPU_REV(2, 1)
add_erratum_entry cortex_x2, ERRATUM(3701772), ERRATA_X2_3701772
check_erratum_ls cortex_x2, ERRATUM(3701772), CPU_REV(2, 1)
workaround_reset_start cortex_x2, CVE(2022, 23960), WORKAROUND_CVE_2022_23960
#if IMAGE_BL31
/*
@ -167,14 +169,12 @@ workaround_reset_end cortex_x2, CVE(2022, 23960)
check_erratum_chosen cortex_x2, CVE(2022, 23960), WORKAROUND_CVE_2022_23960
workaround_reset_start cortex_x2, ERRATUM(2313941), ERRATA_DSU_2313941
errata_dsu_2313941_wa_impl
workaround_reset_end cortex_x2, ERRATUM(2313941)
/* Disable hardware page aggregation. Enables mitigation for `CVE-2024-5660` */
workaround_reset_start cortex_x2, CVE(2024, 5660), WORKAROUND_CVE_2024_5660
sysreg_bit_set CORTEX_X2_CPUECTLR_EL1, BIT(46)
workaround_reset_end cortex_x2, CVE(2024, 5660)
check_erratum_custom_start cortex_x2, ERRATUM(2313941)
check_errata_dsu_2313941_impl
ret
check_erratum_custom_end cortex_x2, ERRATUM(2313941)
check_erratum_ls cortex_x2, CVE(2024, 5660), CPU_REV(2, 1)
/* ----------------------------------------------------
* HW will do the cache maintenance while powering down