remove redundant macro UARTCLK_FREQ and replace it with TC_UARTCLK
in dts.
Change-Id: Id463a9ddc1588278e552ffca3dfb738676229ce7
Signed-off-by: Jagdish Gediya <jagdish.gediya@arm.com>
Signed-off-by: Icen.Zeyada <Icen.Zeyada2@arm.com>
* changes:
feat(tc): add MCN PMU nodes in dts for TC4
feat(tc): add 'kaslr-seed' node in device tree for TC3
feat(tc): enable MCN non-secure access to pmu counters on TC4
feat(tc): define MCN related macros for TC4
Add MCN PMU nodes in dts for TC4 to use MCN PMU driver in
kernel with perf.
Signed-off-by: Jagdish Gediya <jagdish.gediya@arm.com>
Signed-off-by: Icen Zeyada <Icen.Zeyada2@arm.com>
Change-Id: I1a85ba646604336ce3f16c28171589af78f65251
Add 'kaslr-seed' node in device tree for TC3.
Note, TC4 doesn't need to add this node as it can dynamically generate
seed based on CPU arch's RNG_TRAP feature.
Signed-off-by: Leo Yan <leo.yan@arm.com>
Signed-off-by: Icen Zeyada <Icen.Zeyada2@arm.com>
Change-Id: I5c3f857d0f4e81ccd3bacb4c1ab032c8ea6e6873
On STM32MP15 ST boards, RTC clock configuration by OPTEE is not ready
yet. Re-enable it temporary to get LSE as clock source of RTC.
Signed-off-by: Valentin Caron <valentin.caron@foss.st.com>
Change-Id: Ib6071229552e456faffb4fdfc8db9808140d54a7
These dts nodes are used by u-boot MHU/RSE driver to faciliate
communication with RSE over MHU.
FPGA doesn't seem to have the MHU instances which are used to
communicate with RSE so keep rse mhu disabled for fpga.
Signed-off-by: Yu Shihai <yu.shihai@arm.com>
Signed-off-by: Jackson Cooper-Driver <jackson.cooper-driver@arm.com>
Signed-off-by: Jagdish Gediya <jagdish.gediya@arm.com>
Signed-off-by: Icen Zeyada <Icen.Zeyada2@arm.com>
Change-Id: Ib10b3da09626e5beb6d6cd87b1618a143234a5d0
Add DSU PMU node for TC4. DSU PMU interrupt is not connected on TC3
but it is connected on IRQ 290 on TC4, so add interrupt property
specifically for TC4.
Signed-off-by: Jagdish Gediya <jagdish.gediya@arm.com>
Signed-off-by: Icen Zeyada <Icen.Zeyada2@arm.com>
Change-Id: Ib1b810df65004987e9f3cf1bbd5deb5d211f3a17
The component-aware simple encoder has become outdated with the latest
upstream DRM subsystem changes since Linux kernel commit 4cfe5cc02e3f
("drm/arm/komeda: Remove component framework and add a simple encoder")
To address this we introduce a new compilation flag
`TC_DPU_USE_SIMPLE_PANEL` for control panel vs. encoder enablement.
This flag is set when the kernel version is >= 6.6 and 0 when the kernel
version is < 6.6.
We also rename the `vencoder_in` node to `lcd_in` to avoid unnecessary
conditional code for vencoder vs. simple panel enablement.
Signed-off-by: Jagdish Gediya <jagdish.gediya@arm.com>
Signed-off-by: Icen Zeyada <Icen.Zeyada2@arm.com>
Change-Id: Ibb14a56911cfb406b2181a22cc40db58d8ceaa8d
Fix issues in RD1-AE flattened device tree source
- Update GIC GICR register region size to 0x40_0000.
GICR region size = 16 (RDcount) * 64KB frame size * 4 (with GIC v4.1)
- Update cpu_on function ID in psci node.
Use SMC64 version function ID 0xc4000003 instead. Although this
property doesn't actually take effect, align its value with
cpu_suspend selection to avoid any confusion.
Change-Id: Ib0840db45d32f0c8f1eb7dc74dc7d9b4ca6de0c3
Signed-off-by: David Hu <david.hu2@arm.com>
Add a node for AP_REFCLK Non-Secure Generic Timer in device tree, which
acts as a system timer to fix the failure of SystemReady IR ACS BSA
test case 402.
Refer to https://github.com/ARM-software/bsa-acs/blob/v23.09_REL1.0.6\
/docs/arm_bsa_testcase_checklist.rst?plain=1#L115
for more information.
Signed-off-by: Ziad Elhanafy <ziad.elhanafy@arm.com>
Signed-off-by: David Hu <david.hu2@arm.com>
Change-Id: I3e63a5ecfd8c6211f917ca3844b8b7bda208d83a
This clock name was renamed from MCO2_PLL4P to MCO2_PLL4 with the RCC
binding update commit [1]. This file was missed in that update, and the
board fails to compile.
[1]: 52b253bfa2 feat(dt-bindings): new RCC DT bindings
Signed-off-by: Yann Gautier <yann.gautier@st.com>
Change-Id: I215abff1fc275ac1ef6dfb2ac86b9223e6990064
Change the interrupt name "combined-mbx" to "combined", which is the
correct naming defined in the mainline kernel.
Signed-off-by: Leo Yan <leo.yan@arm.com>
Change-Id: I8d2da2dd0e9dac2bed3963efc695a277bb5e14bd
BL31 will need to access a device tree for several configurations (UART,
GIC, OTP mapping...).
Create a BL31 device tree (SOC_FW_CONFIG). It is loaded in DDR, in a
spare area.
Signed-off-by: Yann Gautier <yann.gautier@foss.st.com>
Signed-off-by: Maxime Méré <maxime.mere@foss.st.com>
Change-Id: I320a05859e1aa3dd8db9a274e7201075a8c250c2
Add include for DDR configuration, and reference to OTP storing the
board ID.
Signed-off-by: Yann Gautier <yann.gautier@st.com>
Change-Id: Ie2d5272ecf1dac77b91b2c148ec4dc1fb7b76631
These DT files will be used by STM32MP2 boards. They embed DDR parameters
for DDR4 2x8Gb 2*16bits, at 800MHz or 1200MHz.
Signed-off-by: Yann Gautier <yann.gautier@foss.st.com>
Change-Id: Iec73f9c5028f897624125082bdb591274aad3afc
Complete DDR node with all necessary DDRCTRL (register values) and
DDRPHY (user input values) settings.
Add also name and speed properties.
Signed-off-by: Nicolas Le Bayon <nicolas.le.bayon@st.com>
Change-Id: Ie63f48dcacefe590c68cf6ec694d9e82349cece8
Add the required power supplies for DDR nodes. The power supplies are
provided by STPMIC2 regulators.
Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Change-Id: I951da75a554bc4fbfbc69ea9cd1171d99ed7ce46
With the updated firmware update implementation in the Trusted Services,
it is no longer needed to carve out static memory. Memory will be
allocated dynamically in U-Boot and shared with the firmware update
secure partition of Trusted Services.
Change-Id: I0fb128a458773236ee10526edfa1116b229e4d6e
Signed-off-by: Davidson K <davidson.kumaresan@arm.com>
Signed-off-by: Jackson Cooper-Driver <jackson.cooper-driver@arm.com>
Signed-off-by: Icen Zeyada <Icen.Zeyada2@arm.com>
This commit introduces a new ARM platform-specific build option called
`ARM_FW_CONFIG_LOAD_ENABLE`. This option enables the loading of the
`fw_config` device tree when resetting to the BL2 scenario.
Additionally, the FW_CONFIG image reference has been added to the
fdts/tbbr_cot_descriptors.dtsi file in order to use in the scenario of
RESET_TO_BL2.
Signed-off-by: Divin Raj <divin.raj@arm.com>
Change-Id: I11de497b7dbb1386ed84d939d6fd2a11856e9e1b
It will be used for PMIC on STM32MP257F-EV board.
Signed-off-by: Yann Gautier <yann.gautier@foss.st.com>
Change-Id: I7f95220512de4416323b381fec7c7dcb044c64fd
Update stm32mp251.dtsi SoC DT file to include UART and I2C nodes.
Signed-off-by: Yann Gautier <yann.gautier@foss.st.com>
Signed-off-by: Maxime Méré <maxime.mere@foss.st.com>
Change-Id: I6f52ec2c1735d28ba4a424af71e7eae5b0ac3e0d
This feature is enabled by default using STM32MP_DDR_FIP_IO_STORAGE.
DDR firmware binary is loaded from FIP to SRAM1 which needs to be
mapped.
Only half of the SRAM1 will be allocated to TF-A.
RISAB3 has to be configured to allow access to SRAM1.
Add image ID and update maximum number on platform side also.
Fill related descriptor information, add policy and update numbers.
DDR_TYPE variable is used to identify binary file, and image is now
added in the fiptool command line.
The DDR PHY firmware is not in TF-A repository. It can be found at
https://github.com/STMicroelectronics/stm32-ddr-phy-binary
To ease the selection of the firmware path, STM32MP_DDR_FW_PATH is added
to platform.mk file.
Change-Id: I09ab0a5c63406055a7b5ccd16d65e443de47ca2f
Signed-off-by: Nicolas Le Bayon <nicolas.le.bayon@st.com>
Signed-off-by: Yann Gautier <yann.gautier@st.com>
Signed-off-by: Maxime Méré <maxime.mere@foss.st.com>
Add BL31 load address (beginning on SYSRAM) and size in fw-config DT
file.
Signed-off-by: Yann Gautier <yann.gautier@st.com>
Signed-off-by: Maxime Méré <maxime.mere@foss.st.com>
Change-Id: I2fcd8d326f394090401ac59b47216d59d3e911bc
TC4 adds a new SMMU-700 specifically for the DPU (in the RoS). This is
used as the DPU SMMU instead of the existing SMMU used for both the GPU
and DPU. Update the devicetree to reflect this.
Note that the streamID values have also changes for this new SMMU. This
is because TC4 also updates the new SMMU to use a different streamID for
each DPU port - these must all be added to the device tree.
Change-Id: If2ce9749e40937fd1291346d071b691cfb662f2e
Signed-off-by: Jackson Cooper-Driver <jackson.cooper-driver@arm.com>
Signed-off-by: Leo Yan <leo.yan@arm.com>
A SMMU-700 is used on TC4 for only GPU, on both FVP and FPGA. Add DT
binding for it.
Change-Id: I1b840676fd02c3961d4efdd769f12a4b01d459fb
Signed-off-by: Leo Yan <leo.yan@arm.com>
This patch incorporates the changes for Drage GPU to uses new access
window interface "IRQ_AW". As the interrupt properties are different
between TC4 and other TC platforms, this patch appends the interrupt
properties in platform specific DT binding file.
Change-Id: I2ca505846f03ce64b8e5f02fd202962dbfe39f25
Signed-off-by: Leo Yan <leo.yan@arm.com>
The TC4 uses a new RoS (Virtual Peripherals) and places them at
different address to that in TC3. Add these addresses to the DTS.
Change-Id: Ia62a670e47cdc98b3c113a670a21edc65905cafe
Signed-off-by: Jackson Cooper-Driver <jackson.cooper-driver@arm.com>
Signed-off-by: Leo Yan <leo.yan@arm.com>
Since TC3 and TC4 share most components in the hardware design, they can
reuse the device tree binding. For this reason, this patch extracts the
common modules from tc3.dts and put into the file tc3-4-based.dtsi.
As a result, a new created tc4.dts file includes tc3-4-based.dtsi for
support DT binding for the TC4 platform.
Change-Id: Ib7497162cb131d94a722aeaa14a1a37fb0095829
Signed-off-by: Leo Yan <leo.yan@arm.com>
This is a generic file to be use on all STM32MP2 boards, as what is
done for STM32MP15.
Signed-off-by: Yann Gautier <yann.gautier@st.com>
Change-Id: I4ae0cf0b7d21b1a2072b7ff5e6b98837d603c860
Add dedicated RCC file to define clock tree and include it in
STM32MP257F-EV1 board DT file.
Signed-off-by: Yann Gautier <yann.gautier@st.com>
Change-Id: I259075f34d02534063c95fb571aec6ada480ce5f
Print information about CPU type, package and revision.
SoC revision ID of MP2 family are defined with the OTP 102.
Signed-off-by: Maxime Méré <maxime.mere@foss.st.com>
Signed-off-by: Yann Gautier <yann.gautier@st.com>
Change-Id: I14a95c8a7cb9b06ce32c2e592ae69a1741067e8d
Add sdmmc1 node to support SD-cards on STM32MP257F-EV1 board, and
sdmmc2 node for eMMC.
Signed-off-by: Yann Gautier <yann.gautier@st.com>
Change-Id: I375e35aa6a96719a69df976500915be51c395b00
Add the pins nodes for SD-card or eMMC. Those pins are used on
STM32MP257F-EV1 board.
Signed-off-by: Yann Gautier <yann.gautier@st.com>
Change-Id: I96fe8210502b073bc222a70453bee1863a257c7b
Add the sdmmc1 & sdmmc2 nodes in stm32mp251.dtsi file, to support
eMMC or SD-cards.
To avoid increasing DT size if SD-card or eMMC boot is not selected,
the nodes are removed from DT thanks to stm32mp25-bl2.dtsi overlay.
Signed-off-by: Yann Gautier <yann.gautier@st.com>
Change-Id: I2ed841442b7dddf0c441ae3b3d2462ef535f9951
This will be required for FCONF management on STM32MP2.
Signed-off-by: Yann Gautier <yann.gautier@st.com>
Change-Id: If651a9aa36cdf415f570b2392daa08c198d629d2
Remove the deprecated property "pins-are-numbered" from pinctrl and
pinctrl_z nodes of stm32mp25 soc to conform with the upstream series
of the link below.
Link: https://patchwork.kernel.org/project/linux-arm-kernel/list/?series=69786
Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Change-Id: I1ed98c94c5003bc9903229957cb072da4211238f
Integrate the cot-dt2c tool into build process
for TBBR configuration
Change-Id: I42ccbc96c5c8fd21266200e427306a80236a78aa
Signed-off-by: Xialin Liu <Xialin.Liu@ARM.com>
align the nv counter naming for stm32mp1-cot-descriptor.dtsi file
Change-Id: I8c41c5e323e8bf867e08b4590dfb42e86204ab65
Signed-off-by: Xialin Liu <Xialin.Liu@ARM.com>
Align the naming of nv_counter to nv_ctr in the DTBs
so that they match with the static C files. Update the
binding documentation accordingly. This renaming is beneficial
for the upcoming conversion tool that will convert CoT DT files
to C files.
Change-Id: If65d51ad9fc6445b1ae9937f1691becf8742cf01
Signed-off-by: Xialin Liu <Xialin.Liu@ARM.com>
CPU PMU types are not same for all CPUs on TC platforms, so define the
PMU nodes per micro architectures.
Change-Id: I4e940976cdda9a6eab3e15936c6c41a2bb668c9d
Signed-off-by: Jagdish Gediya <jagdish.gediya@arm.com>
Signed-off-by: Leo Yan <leo.yan@arm.com>
