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Merge changes from topic "mcn" into integration

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* changes:
  feat(tc): add MCN PMU nodes in dts for TC4
  feat(tc): add 'kaslr-seed' node in device tree for TC3
  feat(tc): enable MCN non-secure access to pmu counters on TC4
  feat(tc): define MCN related macros for TC4
This commit is contained in:
Manish V Badarkhe 2024-12-19 14:32:13 +01:00 • committed by TrustedFirmware Code Review
commit 8a7a54b49b
6 changed files with 85 additions and 39 deletions
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20
fdts/tc3-4-base.dtsi
View file

@ -120,4 +120,24 @@
compatible = "arm,dsu-pmu";
cpus = <&CPU0>, <&CPU1>, <&CPU2>, <&CPU3>, <&CPU4>, <&CPU5>, <&CPU6>, <&CPU7>;
};
cs-pmu@0 {
compatible = "arm,coresight-pmu";
reg = <0x0 MCN_PMU_ADDR(0) 0x0 0xffc>;
};
cs-pmu@1 {
compatible = "arm,coresight-pmu";
reg = <0x0 MCN_PMU_ADDR(1) 0x0 0xffc>;
};
cs-pmu@2 {
compatible = "arm,coresight-pmu";
reg = <0x0 MCN_PMU_ADDR(2) 0x0 0xffc>;
};
cs-pmu@3 {
compatible = "arm,coresight-pmu";
reg = <0x0 MCN_PMU_ADDR(3) 0x0 0xffc>;
};
};

25
fdts/tc3.dts
View file

@ -49,24 +49,13 @@
#include "tc3-4-base.dtsi"
/ {
cs-pmu@0 {
compatible = "arm,coresight-pmu";
reg = <0x0 MCN_PMU_ADDR(0) 0x0 0xffc>;
};
cs-pmu@1 {
compatible = "arm,coresight-pmu";
reg = <0x0 MCN_PMU_ADDR(1) 0x0 0xffc>;
};
cs-pmu@2 {
compatible = "arm,coresight-pmu";
reg = <0x0 MCN_PMU_ADDR(2) 0x0 0xffc>;
};
cs-pmu@3 {
compatible = "arm,coresight-pmu";
reg = <0x0 MCN_PMU_ADDR(3) 0x0 0xffc>;
/*
* The kaslr-seed node is a placeholder in DT. In the booting
* sequence, it will be initialized in U-Boot and then later
* used by Linux kernel.
*/
chosen {
kaslr-seed = <0x0 0x0>;
};
spe-pmu-mid {

20
fdts/tc4.dts
View file

@ -71,4 +71,24 @@
dsu-pmu {
interrupts = <GIC_SPI 258 IRQ_TYPE_LEVEL_HIGH 0>;
};
cs-pmu@4 {
compatible = "arm,coresight-pmu";
reg = <0x0 MCN_PMU_ADDR(4) 0x0 0xffc>;
};
cs-pmu@5 {
compatible = "arm,coresight-pmu";
reg = <0x0 MCN_PMU_ADDR(5) 0x0 0xffc>;
};
cs-pmu@6 {
compatible = "arm,coresight-pmu";
reg = <0x0 MCN_PMU_ADDR(6) 0x0 0xffc>;
};
cs-pmu@7 {
compatible = "arm,coresight-pmu";
reg = <0x0 MCN_PMU_ADDR(7) 0x0 0xffc>;
};
};

37
plat/arm/board/tc/include/platform_def.h
View file

@ -463,28 +463,41 @@
#define PLAT_ARM_BOOT_UART_CLK_IN_HZ TC_UARTCLK
#define PLAT_ARM_RUN_UART_CLK_IN_HZ TC_UARTCLK
#if TARGET_PLATFORM == 3
#if (TARGET_PLATFORM == 3) || (TARGET_PLATFORM == 4)
#define NCI_BASE_ADDR UL(0x4F000000)
#ifdef TARGET_FLAVOUR_FPGA
#if (TARGET_PLATFORM == 3) && defined(TARGET_FLAVOUR_FPGA)
#define MCN_ADDRESS_SPACE_SIZE 0x00120000
#else
#define MCN_ADDRESS_SPACE_SIZE 0x00130000
#endif /* TARGET_FLAVOUR_FPGA */
#endif /* (TARGET_PLATFORM == 3) && defined(TARGET_FLAVOUR_FPGA) */
#if TARGET_PLATFORM == 3
#define MCN_OFFSET_IN_NCI 0x00C90000
#define MCN_BASE_ADDR (NCI_BASE_ADDR + MCN_OFFSET_IN_NCI)
#else /* TARGET_PLATFORM == 4 */
#ifdef TARGET_FLAVOUR_FPGA
#define MCN_OFFSET_IN_NCI 0x00420000
#else
#define MCN_OFFSET_IN_NCI 0x00D80000
#endif /* TARGET_FLAVOUR_FPGA */
#endif /* TARGET_PLATFORM == 3 */
#define MCN_BASE_ADDR(n) (NCI_BASE_ADDR + MCN_OFFSET_IN_NCI + \
((n) * MCN_ADDRESS_SPACE_SIZE))
#define MCN_PMU_OFFSET 0x000C4000
#define MCN_MICROARCH_OFFSET 0x000E4000
#define MCN_MICROARCH_BASE_ADDR (MCN_BASE_ADDR + MCN_MICROARCH_OFFSET)
#define MCN_MICROARCH_BASE_ADDR(n) (MCN_BASE_ADDR(n) + \
MCN_MICROARCH_OFFSET)
#define MCN_SCR_OFFSET 0x4
#define MCN_SCR_PMU_BIT 10
#if TARGET_PLATFORM == 3
#define MCN_INSTANCES 4
#define MCN_PMU_ADDR(n) (MCN_BASE_ADDR + \
(n * MCN_ADDRESS_SPACE_SIZE) + \
MCN_PMU_OFFSET)
#else /* TARGET_PLATFORM == 4 */
#define MCN_INSTANCES 8
#endif /* TARGET_PLATFORM == 3 */
#define MCN_PMU_ADDR(n) (MCN_BASE_ADDR(n) + \
MCN_PMU_OFFSET)
#define MCN_MPAM_NS_OFFSET 0x000D0000
#define MCN_MPAM_NS_BASE_ADDR (MCN_BASE_ADDR + MCN_MPAM_NS_OFFSET)
#define MCN_MPAM_NS_BASE_ADDR(n) (MCN_BASE_ADDR(n) + MCN_MPAM_NS_OFFSET)
#define MCN_MPAM_S_OFFSET 0x000D4000
#define MCN_MPAM_S_BASE_ADDR (MCN_BASE_ADDR + MCN_MPAM_S_OFFSET)
#define MCN_MPAM_S_BASE_ADDR(n) (MCN_BASE_ADDR(n) + MCN_MPAM_S_OFFSET)
#define MPAM_SLCCFG_CTL_OFFSET 0x00003018
#define SLC_RDALLOCMODE_SHIFT 8
#define SLC_RDALLOCMODE_MASK (3 << SLC_RDALLOCMODE_SHIFT)
@ -496,7 +509,7 @@
#define SLC_ALLOC_BUS_SIGNAL_ATTR 2
#define MCN_CONFIG_OFFSET 0x204
#define MCN_CONFIG_ADDR (MCN_BASE_ADDR + MCN_CONFIG_OFFSET)
#define MCN_CONFIG_ADDR(n) (MCN_BASE_ADDR(n) + MCN_CONFIG_OFFSET)
#define MCN_CONFIG_SLC_PRESENT_BIT 3
/*
@ -507,7 +520,7 @@
*/
#define CPUECTLR_EL1 CORTEX_A520_CPUECTLR_EL1
#define CPUECTLR_EL1_EXTLLC_BIT CORTEX_A520_CPUECTLR_EL1_EXTLLC_BIT
#endif /* TARGET_PLATFORM == 3 */
#endif /* (TARGET_PLATFORM == 3) || (TARGET_PLATFORM == 4) */
#define CPUACTLR_CLUSTERPMUEN (ULL(1) << 12)

2
plat/arm/board/tc/include/tc_helpers.S
View file

@ -54,7 +54,7 @@ endfunc plat_arm_calc_core_pos
func mark_extllc_presence
#ifdef MCN_CONFIG_ADDR
mov_imm x0, (MCN_CONFIG_ADDR)
mov_imm x0, (MCN_CONFIG_ADDR(0))
ldr w1, [x0]
ubfx x1, x1, #MCN_CONFIG_SLC_PRESENT_BIT, #1
sysreg_bitfield_insert_from_gpr CPUECTLR_EL1, x1, \

20
plat/arm/board/tc/tc_bl31_setup.c
View file

@ -72,19 +72,21 @@ static scmi_channel_plat_info_t tc_scmi_plat_info = {
};
#endif
#if TARGET_PLATFORM == 3
#if (TARGET_PLATFORM == 3) || (TARGET_PLATFORM == 4)
static void enable_ns_mcn_pmu(void)
{
/*
* Enable non-secure access to MCN PMU registers
*/
for (int i = 0; i < MCN_INSTANCES; i++) {
uintptr_t mcn_scr = MCN_MICROARCH_BASE_ADDR + MCN_SCR_OFFSET +
(i * MCN_ADDRESS_SPACE_SIZE);
uintptr_t mcn_scr = MCN_MICROARCH_BASE_ADDR(i) +
MCN_SCR_OFFSET;
mmio_setbits_32(mcn_scr, 1 << MCN_SCR_PMU_BIT);
}
}
#endif /* (TARGET_PLATFORM == 3) || (TARGET_PLATFORM == 4) */
#if TARGET_PLATFORM == 3
static void set_mcn_slc_alloc_mode(void)
{
/*
@ -93,10 +95,10 @@ static void set_mcn_slc_alloc_mode(void)
* attribute from interface).
*/
for (int i = 0; i < MCN_INSTANCES; i++) {
uintptr_t slccfg_ctl_ns = MCN_MPAM_NS_BASE_ADDR +
(i * MCN_ADDRESS_SPACE_SIZE) + MPAM_SLCCFG_CTL_OFFSET;
uintptr_t slccfg_ctl_s = MCN_MPAM_S_BASE_ADDR +
(i * MCN_ADDRESS_SPACE_SIZE) + MPAM_SLCCFG_CTL_OFFSET;
uintptr_t slccfg_ctl_ns = MCN_MPAM_NS_BASE_ADDR(i) +
MPAM_SLCCFG_CTL_OFFSET;
uintptr_t slccfg_ctl_s = MCN_MPAM_S_BASE_ADDR(i) +
MPAM_SLCCFG_CTL_OFFSET;
mmio_clrsetbits_32(slccfg_ctl_ns,
(SLC_RDALLOCMODE_MASK | SLC_WRALLOCMODE_MASK),
@ -113,8 +115,10 @@ static void set_mcn_slc_alloc_mode(void)
void bl31_platform_setup(void)
{
tc_bl31_common_platform_setup();
#if TARGET_PLATFORM == 3
#if (TARGET_PLATFORM == 3) || (TARGET_PLATFORM == 4)
enable_ns_mcn_pmu();
#endif /* (TARGET_PLATFORM == 3) || (TARGET_PLATFORM == 4) */
#if TARGET_PLATFORM == 3
set_mcn_slc_alloc_mode();
plat_arm_ni_setup(NCI_BASE_ADDR);
#endif