From 8f61c20457c8e683b9c6b2a3f3c4ebcf4b1a5371 Mon Sep 17 00:00:00 2001 From: Jagdish Gediya Date: Wed, 19 Jun 2024 08:50:45 +0000 Subject: [PATCH 1/4] feat(tc): define MCN related macros for TC4 Define MCN related macros for TC4 to add TC4 specific MCN PMU nodes in dts and to enable MCN PMU NS access in further commits. Signed-off-by: Jagdish Gediya Signed-off-by: Icen Zeyada Change-Id: Ifc02fcd833888a9953fac404585468316aa0168c --- plat/arm/board/tc/include/platform_def.h | 37 ++++++++++++++++-------- plat/arm/board/tc/include/tc_helpers.S | 2 +- plat/arm/board/tc/tc_bl31_setup.c | 12 ++++---- 3 files changed, 32 insertions(+), 19 deletions(-) diff --git a/plat/arm/board/tc/include/platform_def.h b/plat/arm/board/tc/include/platform_def.h index 7f24f843a..5a226284c 100644 --- a/plat/arm/board/tc/include/platform_def.h +++ b/plat/arm/board/tc/include/platform_def.h @@ -463,28 +463,41 @@ #define PLAT_ARM_BOOT_UART_CLK_IN_HZ TC_UARTCLK #define PLAT_ARM_RUN_UART_CLK_IN_HZ TC_UARTCLK -#if TARGET_PLATFORM == 3 +#if (TARGET_PLATFORM == 3) || (TARGET_PLATFORM == 4) #define NCI_BASE_ADDR UL(0x4F000000) -#ifdef TARGET_FLAVOUR_FPGA +#if (TARGET_PLATFORM == 3) && defined(TARGET_FLAVOUR_FPGA) #define MCN_ADDRESS_SPACE_SIZE 0x00120000 #else #define MCN_ADDRESS_SPACE_SIZE 0x00130000 -#endif /* TARGET_FLAVOUR_FPGA */ +#endif /* (TARGET_PLATFORM == 3) && defined(TARGET_FLAVOUR_FPGA) */ +#if TARGET_PLATFORM == 3 #define MCN_OFFSET_IN_NCI 0x00C90000 -#define MCN_BASE_ADDR (NCI_BASE_ADDR + MCN_OFFSET_IN_NCI) +#else /* TARGET_PLATFORM == 4 */ +#ifdef TARGET_FLAVOUR_FPGA +#define MCN_OFFSET_IN_NCI 0x00420000 +#else +#define MCN_OFFSET_IN_NCI 0x00D80000 +#endif /* TARGET_FLAVOUR_FPGA */ +#endif /* TARGET_PLATFORM == 3 */ +#define MCN_BASE_ADDR(n) (NCI_BASE_ADDR + MCN_OFFSET_IN_NCI + \ + ((n) * MCN_ADDRESS_SPACE_SIZE)) #define MCN_PMU_OFFSET 0x000C4000 #define MCN_MICROARCH_OFFSET 0x000E4000 -#define MCN_MICROARCH_BASE_ADDR (MCN_BASE_ADDR + MCN_MICROARCH_OFFSET) +#define MCN_MICROARCH_BASE_ADDR(n) (MCN_BASE_ADDR(n) + \ + MCN_MICROARCH_OFFSET) #define MCN_SCR_OFFSET 0x4 #define MCN_SCR_PMU_BIT 10 +#if TARGET_PLATFORM == 3 #define MCN_INSTANCES 4 -#define MCN_PMU_ADDR(n) (MCN_BASE_ADDR + \ - (n * MCN_ADDRESS_SPACE_SIZE) + \ - MCN_PMU_OFFSET) +#else /* TARGET_PLATFORM == 4 */ +#define MCN_INSTANCES 8 +#endif /* TARGET_PLATFORM == 3 */ +#define MCN_PMU_ADDR(n) (MCN_BASE_ADDR(n) + \ + MCN_PMU_OFFSET) #define MCN_MPAM_NS_OFFSET 0x000D0000 -#define MCN_MPAM_NS_BASE_ADDR (MCN_BASE_ADDR + MCN_MPAM_NS_OFFSET) +#define MCN_MPAM_NS_BASE_ADDR(n) (MCN_BASE_ADDR(n) + MCN_MPAM_NS_OFFSET) #define MCN_MPAM_S_OFFSET 0x000D4000 -#define MCN_MPAM_S_BASE_ADDR (MCN_BASE_ADDR + MCN_MPAM_S_OFFSET) +#define MCN_MPAM_S_BASE_ADDR(n) (MCN_BASE_ADDR(n) + MCN_MPAM_S_OFFSET) #define MPAM_SLCCFG_CTL_OFFSET 0x00003018 #define SLC_RDALLOCMODE_SHIFT 8 #define SLC_RDALLOCMODE_MASK (3 << SLC_RDALLOCMODE_SHIFT) @@ -496,7 +509,7 @@ #define SLC_ALLOC_BUS_SIGNAL_ATTR 2 #define MCN_CONFIG_OFFSET 0x204 -#define MCN_CONFIG_ADDR (MCN_BASE_ADDR + MCN_CONFIG_OFFSET) +#define MCN_CONFIG_ADDR(n) (MCN_BASE_ADDR(n) + MCN_CONFIG_OFFSET) #define MCN_CONFIG_SLC_PRESENT_BIT 3 /* @@ -507,7 +520,7 @@ */ #define CPUECTLR_EL1 CORTEX_A520_CPUECTLR_EL1 #define CPUECTLR_EL1_EXTLLC_BIT CORTEX_A520_CPUECTLR_EL1_EXTLLC_BIT -#endif /* TARGET_PLATFORM == 3 */ +#endif /* (TARGET_PLATFORM == 3) || (TARGET_PLATFORM == 4) */ #define CPUACTLR_CLUSTERPMUEN (ULL(1) << 12) diff --git a/plat/arm/board/tc/include/tc_helpers.S b/plat/arm/board/tc/include/tc_helpers.S index 48ca16c04..1fde9e921 100644 --- a/plat/arm/board/tc/include/tc_helpers.S +++ b/plat/arm/board/tc/include/tc_helpers.S @@ -54,7 +54,7 @@ endfunc plat_arm_calc_core_pos func mark_extllc_presence #ifdef MCN_CONFIG_ADDR - mov_imm x0, (MCN_CONFIG_ADDR) + mov_imm x0, (MCN_CONFIG_ADDR(0)) ldr w1, [x0] ubfx x1, x1, #MCN_CONFIG_SLC_PRESENT_BIT, #1 sysreg_bitfield_insert_from_gpr CPUECTLR_EL1, x1, \ diff --git a/plat/arm/board/tc/tc_bl31_setup.c b/plat/arm/board/tc/tc_bl31_setup.c index 0afc73bca..f014bae10 100644 --- a/plat/arm/board/tc/tc_bl31_setup.c +++ b/plat/arm/board/tc/tc_bl31_setup.c @@ -79,8 +79,8 @@ static void enable_ns_mcn_pmu(void) * Enable non-secure access to MCN PMU registers */ for (int i = 0; i < MCN_INSTANCES; i++) { - uintptr_t mcn_scr = MCN_MICROARCH_BASE_ADDR + MCN_SCR_OFFSET + - (i * MCN_ADDRESS_SPACE_SIZE); + uintptr_t mcn_scr = MCN_MICROARCH_BASE_ADDR(i) + + MCN_SCR_OFFSET; mmio_setbits_32(mcn_scr, 1 << MCN_SCR_PMU_BIT); } } @@ -93,10 +93,10 @@ static void set_mcn_slc_alloc_mode(void) * attribute from interface). */ for (int i = 0; i < MCN_INSTANCES; i++) { - uintptr_t slccfg_ctl_ns = MCN_MPAM_NS_BASE_ADDR + - (i * MCN_ADDRESS_SPACE_SIZE) + MPAM_SLCCFG_CTL_OFFSET; - uintptr_t slccfg_ctl_s = MCN_MPAM_S_BASE_ADDR + - (i * MCN_ADDRESS_SPACE_SIZE) + MPAM_SLCCFG_CTL_OFFSET; + uintptr_t slccfg_ctl_ns = MCN_MPAM_NS_BASE_ADDR(i) + + MPAM_SLCCFG_CTL_OFFSET; + uintptr_t slccfg_ctl_s = MCN_MPAM_S_BASE_ADDR(i) + + MPAM_SLCCFG_CTL_OFFSET; mmio_clrsetbits_32(slccfg_ctl_ns, (SLC_RDALLOCMODE_MASK | SLC_WRALLOCMODE_MASK), From d1062c472a2976a03c74479eb18327e46f604f6c Mon Sep 17 00:00:00 2001 From: Jagdish Gediya Date: Wed, 19 Jun 2024 08:57:47 +0000 Subject: [PATCH 2/4] feat(tc): enable MCN non-secure access to pmu counters on TC4 MCN PMU counters are by default non-accesible from non-secure world, so enable the non-secure access to those PMU counters so that linux perf driver can read them. Signed-off-by: Jagdish Gediya Signed-off-by: Icen Zeyada Change-Id: I1cf1f88f97e9062592fd5603a78fd36f15a15f89 --- plat/arm/board/tc/tc_bl31_setup.c | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-) diff --git a/plat/arm/board/tc/tc_bl31_setup.c b/plat/arm/board/tc/tc_bl31_setup.c index f014bae10..bc8f5ec7f 100644 --- a/plat/arm/board/tc/tc_bl31_setup.c +++ b/plat/arm/board/tc/tc_bl31_setup.c @@ -72,7 +72,7 @@ static scmi_channel_plat_info_t tc_scmi_plat_info = { }; #endif -#if TARGET_PLATFORM == 3 +#if (TARGET_PLATFORM == 3) || (TARGET_PLATFORM == 4) static void enable_ns_mcn_pmu(void) { /* @@ -84,7 +84,9 @@ static void enable_ns_mcn_pmu(void) mmio_setbits_32(mcn_scr, 1 << MCN_SCR_PMU_BIT); } } +#endif /* (TARGET_PLATFORM == 3) || (TARGET_PLATFORM == 4) */ +#if TARGET_PLATFORM == 3 static void set_mcn_slc_alloc_mode(void) { /* @@ -113,8 +115,10 @@ static void set_mcn_slc_alloc_mode(void) void bl31_platform_setup(void) { tc_bl31_common_platform_setup(); -#if TARGET_PLATFORM == 3 +#if (TARGET_PLATFORM == 3) || (TARGET_PLATFORM == 4) enable_ns_mcn_pmu(); +#endif /* (TARGET_PLATFORM == 3) || (TARGET_PLATFORM == 4) */ +#if TARGET_PLATFORM == 3 set_mcn_slc_alloc_mode(); plat_arm_ni_setup(NCI_BASE_ADDR); #endif From 2d967e92e00fe05f0c1ecaddf414d50078050f9d Mon Sep 17 00:00:00 2001 From: Leo Yan Date: Fri, 31 May 2024 12:21:58 +0100 Subject: [PATCH 3/4] feat(tc): add 'kaslr-seed' node in device tree for TC3 Add 'kaslr-seed' node in device tree for TC3. Note, TC4 doesn't need to add this node as it can dynamically generate seed based on CPU arch's RNG_TRAP feature. Signed-off-by: Leo Yan Signed-off-by: Icen Zeyada Change-Id: I5c3f857d0f4e81ccd3bacb4c1ab032c8ea6e6873 --- fdts/tc3.dts | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/fdts/tc3.dts b/fdts/tc3.dts index 3b02f91df..bce1a54b5 100644 --- a/fdts/tc3.dts +++ b/fdts/tc3.dts @@ -49,6 +49,15 @@ #include "tc3-4-base.dtsi" / { + /* + * The kaslr-seed node is a placeholder in DT. In the booting + * sequence, it will be initialized in U-Boot and then later + * used by Linux kernel. + */ + chosen { + kaslr-seed = <0x0 0x0>; + }; + cs-pmu@0 { compatible = "arm,coresight-pmu"; reg = <0x0 MCN_PMU_ADDR(0) 0x0 0xffc>; From 624deb0825cf6b7e27165edf182bd075e58ee2ff Mon Sep 17 00:00:00 2001 From: Jagdish Gediya Date: Wed, 19 Jun 2024 08:52:48 +0000 Subject: [PATCH 4/4] feat(tc): add MCN PMU nodes in dts for TC4 Add MCN PMU nodes in dts for TC4 to use MCN PMU driver in kernel with perf. Signed-off-by: Jagdish Gediya Signed-off-by: Icen Zeyada Change-Id: I1a85ba646604336ce3f16c28171589af78f65251 --- fdts/tc3-4-base.dtsi | 20 ++++++++++++++++++++ fdts/tc3.dts | 20 -------------------- fdts/tc4.dts | 20 ++++++++++++++++++++ 3 files changed, 40 insertions(+), 20 deletions(-) diff --git a/fdts/tc3-4-base.dtsi b/fdts/tc3-4-base.dtsi index 5ccfebb3d..c7f3084ba 100644 --- a/fdts/tc3-4-base.dtsi +++ b/fdts/tc3-4-base.dtsi @@ -120,4 +120,24 @@ compatible = "arm,dsu-pmu"; cpus = <&CPU0>, <&CPU1>, <&CPU2>, <&CPU3>, <&CPU4>, <&CPU5>, <&CPU6>, <&CPU7>; }; + + cs-pmu@0 { + compatible = "arm,coresight-pmu"; + reg = <0x0 MCN_PMU_ADDR(0) 0x0 0xffc>; + }; + + cs-pmu@1 { + compatible = "arm,coresight-pmu"; + reg = <0x0 MCN_PMU_ADDR(1) 0x0 0xffc>; + }; + + cs-pmu@2 { + compatible = "arm,coresight-pmu"; + reg = <0x0 MCN_PMU_ADDR(2) 0x0 0xffc>; + }; + + cs-pmu@3 { + compatible = "arm,coresight-pmu"; + reg = <0x0 MCN_PMU_ADDR(3) 0x0 0xffc>; + }; }; diff --git a/fdts/tc3.dts b/fdts/tc3.dts index bce1a54b5..b8fe58750 100644 --- a/fdts/tc3.dts +++ b/fdts/tc3.dts @@ -58,26 +58,6 @@ kaslr-seed = <0x0 0x0>; }; - cs-pmu@0 { - compatible = "arm,coresight-pmu"; - reg = <0x0 MCN_PMU_ADDR(0) 0x0 0xffc>; - }; - - cs-pmu@1 { - compatible = "arm,coresight-pmu"; - reg = <0x0 MCN_PMU_ADDR(1) 0x0 0xffc>; - }; - - cs-pmu@2 { - compatible = "arm,coresight-pmu"; - reg = <0x0 MCN_PMU_ADDR(2) 0x0 0xffc>; - }; - - cs-pmu@3 { - compatible = "arm,coresight-pmu"; - reg = <0x0 MCN_PMU_ADDR(3) 0x0 0xffc>; - }; - spe-pmu-mid { status = "okay"; }; diff --git a/fdts/tc4.dts b/fdts/tc4.dts index 8b73b4990..5ab58d571 100644 --- a/fdts/tc4.dts +++ b/fdts/tc4.dts @@ -71,4 +71,24 @@ dsu-pmu { interrupts = ; }; + + cs-pmu@4 { + compatible = "arm,coresight-pmu"; + reg = <0x0 MCN_PMU_ADDR(4) 0x0 0xffc>; + }; + + cs-pmu@5 { + compatible = "arm,coresight-pmu"; + reg = <0x0 MCN_PMU_ADDR(5) 0x0 0xffc>; + }; + + cs-pmu@6 { + compatible = "arm,coresight-pmu"; + reg = <0x0 MCN_PMU_ADDR(6) 0x0 0xffc>; + }; + + cs-pmu@7 { + compatible = "arm,coresight-pmu"; + reg = <0x0 MCN_PMU_ADDR(7) 0x0 0xffc>; + }; };