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fix(tc): correct CPU PMU binding

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CPU PMU types are not same for all CPUs on TC platforms, so define the
PMU nodes per micro architectures.

Change-Id: I4e940976cdda9a6eab3e15936c6c41a2bb668c9d
Signed-off-by: Jagdish Gediya <jagdish.gediya@arm.com>
Signed-off-by: Leo Yan <leo.yan@arm.com>
This commit is contained in:
Jagdish Gediya 2024-04-24 15:20:21 +01:00 • committed by Leo Yan
parent 77080f6aaf
commit 7aca660c4e
3 changed files with 24 additions and 20 deletions
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19
fdts/tc-base.dtsi
View file

@ -265,9 +265,22 @@
method = "smc";
};
cpu-pmu {
compatible = "arm,armv8-pmuv3";
interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH 0>;
cpu-pmu-little {
compatible = LIT_CPU_PMU_COMPATIBLE;
interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH &ppi_partition_little>;
status = "okay";
};
cpu-pmu-mid {
compatible = MID_CPU_PMU_COMPATIBLE;
interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH &ppi_partition_mid>;
status = "okay";
};
cpu-pmu-big {
compatible = BIG_CPU_PMU_COMPATIBLE;
interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH &ppi_partition_big>;
status = "okay";
};
sram: sram@6000000 {

16
fdts/tc2.dts
View file

@ -31,6 +31,10 @@
#define MHU_RX_INT_NUM 317
#define MHU_RX_INT_NAME "mhu_rx"
#define LIT_CPU_PMU_COMPATIBLE "arm,cortex-a520-pmu"
#define MID_CPU_PMU_COMPATIBLE "arm,cortex-a720-pmu"
#define BIG_CPU_PMU_COMPATIBLE "arm,cortex-x4-pmu"
#define MPAM_ADDR 0x1 0x00010000 /* 0x1_0001_0000 */
#define UARTCLK_FREQ 5000000
@ -193,18 +197,6 @@
};
#endif /* TARGET_FLAVOUR_FPGA */
cpu-pmu {
#if TARGET_FLAVOUR_FPGA
interrupt-affinity = <&CPU0>, <&CPU1>, <&CPU2>, <&CPU3>,
<&CPU4>, <&CPU5>, <&CPU6>, <&CPU7>,
<&CPU8>, <&CPU9>, <&CPU10>, <&CPU11>,
<&CPU12>, <&CPU13>;
#else
interrupt-affinity = <&CPU0>, <&CPU1>, <&CPU2>, <&CPU3>,
<&CPU4>, <&CPU5>, <&CPU6>, <&CPU7>;
#endif
};
cmn-pmu {
compatible = "arm,ci-700";
reg = <0x0 0x50000000 0x0 0x10000000>;

9
fdts/tc3.dts
View file

@ -25,6 +25,10 @@
#define MHU_RX_INT_NUM 300
#define MHU_RX_INT_NAME "combined-mbx"
#define LIT_CPU_PMU_COMPATIBLE "arm,cortex-a520-pmu"
#define MID_CPU_PMU_COMPATIBLE "arm,cortex-a725-pmu"
#define BIG_CPU_PMU_COMPATIBLE "arm,cortex-x925-pmu"
#define MPAM_ADDR 0x0 0x5f010000 /* 0x5f01_0000 */
#define UARTCLK_FREQ 3750000
@ -67,11 +71,6 @@
};
};
cpu-pmu {
interrupt-affinity = <&CPU0>, <&CPU1>, <&CPU2>, <&CPU3>,
<&CPU4>, <&CPU5>, <&CPU6>, <&CPU7>;
};
cs-pmu@0 {
compatible = "arm,coresight-pmu";
reg = <0x0 MCN_PMU_ADDR(0) 0x0 0xffc>;