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refactor(tc): remove redundant macro UARTCLK_FREQ

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remove redundant macro UARTCLK_FREQ and replace it with TC_UARTCLK
in dts.

Change-Id: Id463a9ddc1588278e552ffca3dfb738676229ce7
Signed-off-by: Jagdish Gediya <jagdish.gediya@arm.com>
Signed-off-by: Icen.Zeyada <Icen.Zeyada2@arm.com>
This commit is contained in:
Jagdish Gediya 2024-06-28 11:00:18 +00:00 • committed by Icen.Zeyada
parent 08c3d26dc1
commit 25264e292c
4 changed files with 6 additions and 8 deletions
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2
fdts/tc-base.dtsi
View file

@ -387,7 +387,7 @@
soc_uartclk: uartclk {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <UARTCLK_FREQ>;
clock-frequency = <TC_UARTCLK>;
clock-output-names = "uartclk";
};

1
fdts/tc2.dts
View file

@ -36,7 +36,6 @@
#define BIG_CPU_PMU_COMPATIBLE "arm,cortex-x4-pmu"
#define MPAM_ADDR 0x1 0x00010000 /* 0x1_0001_0000 */
#define UARTCLK_FREQ 5000000
#define DPU_ADDR 2cc00000
#define DPU_IRQ 69

1
fdts/tc3-4-base.dtsi
View file

@ -18,7 +18,6 @@
#define MHU_RX_INT_NAME "combined"
#define MPAM_ADDR 0x0 0x5f010000 /* 0x5f01_0000 */
#define UARTCLK_FREQ 3750000
#if TARGET_FLAVOUR_FVP
#define DPU_ADDR 4000000000

10
plat/arm/board/tc/include/platform_def.h
View file

@ -443,16 +443,16 @@
#undef PLAT_ARM_BOOT_UART_CLK_IN_HZ
#undef PLAT_ARM_RUN_UART_CLK_IN_HZ
#if TARGET_FLAVOUR_FVP
#define PLAT_ARM_BOOT_UART_BASE TC_UART1
#define TC_UARTCLK 7372800
#else /* TARGET_FLAVOUR_FPGA */
#define PLAT_ARM_BOOT_UART_BASE TC_UART0
#if TARGET_PLATFORM <= 2
#define TC_UARTCLK 5000000
#elif TARGET_PLATFORM >= 3
#define TC_UARTCLK 3750000
#endif /* TARGET_PLATFORM >= 3 */
#if TARGET_FLAVOUR_FVP
#define PLAT_ARM_BOOT_UART_BASE TC_UART1
#else /* TARGET_FLAVOUR_FPGA */
#define PLAT_ARM_BOOT_UART_BASE TC_UART0
#undef ARM_CONSOLE_BAUDRATE
#define ARM_CONSOLE_BAUDRATE 38400
#endif /* TARGET_FLAVOUR_FPGA */