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feat(tc): update DT for Drage GPU

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This patch incorporates the changes for Drage GPU to uses new access
window interface "IRQ_AW". As the interrupt properties are different
between TC4 and other TC platforms, this patch appends the interrupt
properties in platform specific DT binding file.

Change-Id: I2ca505846f03ce64b8e5f02fd202962dbfe39f25
Signed-off-by: Leo Yan <leo.yan@arm.com>
This commit is contained in:
Leo Yan 2024-04-22 18:02:52 +01:00
parent 9face2123a
commit b3a4f8cfcf
4 changed files with 15 additions and 4 deletions
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4
fdts/tc-base.dtsi
View file

@ -495,10 +495,6 @@
gpu: gpu@2d000000 {
compatible = "arm,mali-midgard";
reg = <0x0 0x2d000000 0x0 0x200000>;
interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH 0>,
<GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH 0>,
<GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH 0>;
interrupt-names = "JOB", "MMU", "GPU";
clocks = <&gpu_core_clk>;
clock-names = "shadercores";
#if TC_SCMI_PD_CTRL_EN

4
fdts/tc2.dts
View file

@ -291,6 +291,10 @@
};
gpu: gpu@2d000000 {
interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH 0>,
<GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH 0>,
<GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH 0>;
interrupt-names = "JOB", "MMU", "GPU";
iommus = <&smmu_700 0x200>;
};
};

4
fdts/tc3.dts
View file

@ -110,6 +110,10 @@
};
gpu: gpu@2d000000 {
interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH 0>,
<GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH 0>,
<GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH 0>;
interrupt-names = "JOB", "MMU", "GPU";
#if TARGET_FLAVOUR_FVP
iommus = <&smmu_700 0x200>;
#endif

7
fdts/tc4.dts
View file

@ -44,3 +44,10 @@
#include "tc-fpga.dtsi"
#endif /* TARGET_FLAVOUR_FVP */
#include "tc3-4-base.dtsi"
/ {
gpu: gpu@2d000000 {
interrupts = <GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH 0>;
interrupt-names = "IRQAW";
};
};