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feat(stm32mp2-fdts): add clock tree for STM32MP257F-EV1

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Add dedicated RCC file to define clock tree and include it in
STM32MP257F-EV1 board DT file.

Signed-off-by: Yann Gautier <yann.gautier@st.com>
Change-Id: I259075f34d02534063c95fb571aec6ada480ce5f
This commit is contained in:
Yann Gautier 2022-11-03 17:25:40 +01:00 • committed by Yann Gautier
parent 5e0be8c024
commit 293a4f3def
2 changed files with 99 additions and 0 deletions
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97
fdts/stm32mp257f-ev1-ca35tdcid-rcc.dtsi Normal file
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@ -0,0 +1,97 @@
// SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause)
/*
* Copyright (C) STMicroelectronics 2024 - All Rights Reserved
* Author: Loic Pallardy loic.pallardy@foss.st.com for STMicroelectronics.
*/
/*
* STM32MP25 Clock tree device tree configuration
* Project : open
* Generated by XLmx tool version 2.2 - 2/27/2024 11:46:16 AM
*/
&clk_hse {
clock-frequency = <40000000>;
};
&clk_hsi {
clock-frequency = <64000000>;
};
&clk_lse {
clock-frequency = <32768>;
};
&clk_lsi {
clock-frequency = <32000>;
};
&clk_msi {
clock-frequency = <16000000>;
};
&rcc {
st,busclk = <
DIV_CFG(DIV_LSMCU, 1)
DIV_CFG(DIV_APB1, 0)
DIV_CFG(DIV_APB2, 0)
DIV_CFG(DIV_APB3, 0)
DIV_CFG(DIV_APB4, 0)
DIV_CFG(DIV_APBDBG, 0)
>;
st,flexgen = <
FLEXGEN_CFG(0, XBAR_SRC_PLL4, 0, 2)
FLEXGEN_CFG(1, XBAR_SRC_PLL4, 0, 5)
FLEXGEN_CFG(2, XBAR_SRC_PLL4, 0, 1)
FLEXGEN_CFG(4, XBAR_SRC_PLL4, 0, 3)
FLEXGEN_CFG(5, XBAR_SRC_PLL4, 0, 2)
FLEXGEN_CFG(8, XBAR_SRC_HSI_KER, 0, 0)
FLEXGEN_CFG(48, XBAR_SRC_PLL5, 0, 3)
FLEXGEN_CFG(51, XBAR_SRC_PLL4, 0, 5)
FLEXGEN_CFG(52, XBAR_SRC_PLL4, 0, 5)
FLEXGEN_CFG(58, XBAR_SRC_HSE, 0, 1)
FLEXGEN_CFG(63, XBAR_SRC_PLL4, 0, 2)
>;
st,kerclk = <
MUX_CFG(MUX_USB2PHY1, MUX_USB2PHY1_FLEX57)
MUX_CFG(MUX_USB2PHY2, MUX_USB2PHY2_FLEX58)
>;
pll1: st,pll-1 {
st,pll = <&pll1_cfg_1200Mhz>;
pll1_cfg_1200Mhz: pll1-cfg-1200Mhz {
cfg = <30 1 1 1>;
src = <MUX_CFG(MUX_MUXSEL5, MUXSEL_HSE)>;
};
};
pll2: st,pll-2 {
st,pll = <&pll2_cfg_600Mhz>;
pll2_cfg_600Mhz: pll2-cfg-600Mhz {
cfg = <30 1 1 2>;
src = <MUX_CFG(MUX_MUXSEL6, MUXSEL_HSE)>;
};
};
pll4: st,pll-4 {
st,pll = <&pll4_cfg_1200Mhz>;
pll4_cfg_1200Mhz: pll4-cfg-1200Mhz {
cfg = <30 1 1 1>;
src = <MUX_CFG(MUX_MUXSEL0, MUXSEL_HSE)>;
};
};
pll5: st,pll-5 {
st,pll = <&pll5_cfg_532Mhz>;
pll5_cfg_532Mhz: pll5-cfg-532Mhz {
cfg = <133 5 1 2>;
src = <MUX_CFG(MUX_MUXSEL1, MUXSEL_HSE)>;
};
};
};

2
fdts/stm32mp257f-ev1.dts
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@ -6,8 +6,10 @@
/dts-v1/;
#include <dt-bindings/clock/stm32mp25-clksrc.h>
#include "stm32mp257.dtsi"
#include "stm32mp25xf.dtsi"
#include "stm32mp257f-ev1-ca35tdcid-rcc.dtsi"
#include "stm32mp25-pinctrl.dtsi"
#include "stm32mp25xxai-pinctrl.dtsi"