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https://github.com/ARM-software/arm-trusted-firmware.git
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feat(rd1ae): add device tree files
This commit Add FW_CONFIG and HW_CONFIG device trees Signed-off-by: Divin Raj <divin.raj@arm.com> Change-Id: Ia6cbf06def8ec9b74ef9040bab801278a3117899
This commit is contained in:
Divin Raj
parent
f661c74b52
commit
bb7c7e7130
4 changed files with 453 additions and 0 deletions
416
fdts/rd1ae.dts
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416
fdts/rd1ae.dts
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/*
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* Copyright (c) 2024, Arm Limited. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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/dts-v1/;
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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/ {
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model = "RD-1 AE";
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compatible = "arm,rd1ae", "arm,neoverse";
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interrupt-parent = <&gic>;
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#address-cells = <2>;
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#size-cells = <2>;
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chosen {
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stdout-path = &soc_serial0;
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};
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cpus {
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#address-cells = <2>;
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#size-cells = <0>;
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cpu0: cpu@0 {
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device_type = "cpu";
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compatible = "arm,neoverse-v3";
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reg = <0x0 0x0>;
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enable-method = "psci";
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i-cache-size = <0x10000>;
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i-cache-line-size = <0x40>;
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i-cache-sets = <0x100>;
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d-cache-size = <0x10000>;
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d-cache-line-size = <0x40>;
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d-cache-sets = <0x100>;
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};
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cpu1: cpu@10000 {
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device_type = "cpu";
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compatible = "arm,neoverse-v3";
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reg = <0x0 0x10000>;
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enable-method = "psci";
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i-cache-size = <0x10000>;
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i-cache-line-size = <0x40>;
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i-cache-sets = <0x100>;
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d-cache-size = <0x10000>;
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d-cache-line-size = <0x40>;
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d-cache-sets = <0x100>;
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};
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cpu2: cpu@20000 {
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device_type = "cpu";
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compatible = "arm,neoverse-v3";
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reg = <0x0 0x20000>;
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enable-method = "psci";
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i-cache-size = <0x10000>;
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i-cache-line-size = <0x40>;
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i-cache-sets = <0x100>;
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d-cache-size = <0x10000>;
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d-cache-line-size = <0x40>;
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d-cache-sets = <0x100>;
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};
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cpu3: cpu@30000 {
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device_type = "cpu";
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compatible = "arm,neoverse-v3";
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reg = <0x0 0x30000>;
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enable-method = "psci";
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i-cache-size = <0x10000>;
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i-cache-line-size = <0x40>;
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i-cache-sets = <0x100>;
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d-cache-size = <0x10000>;
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d-cache-line-size = <0x40>;
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d-cache-sets = <0x100>;
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};
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cpu4: cpu@40000 {
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device_type = "cpu";
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compatible = "arm,neoverse-v3";
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reg = <0x0 0x40000>;
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enable-method = "psci";
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i-cache-size = <0x10000>;
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i-cache-line-size = <0x40>;
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i-cache-sets = <0x100>;
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d-cache-size = <0x10000>;
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d-cache-line-size = <0x40>;
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d-cache-sets = <0x100>;
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};
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cpu5: cpu@50000 {
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device_type = "cpu";
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compatible = "arm,neoverse-v3";
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reg = <0x0 0x50000>;
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enable-method = "psci";
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i-cache-size = <0x10000>;
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i-cache-line-size = <0x40>;
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i-cache-sets = <0x100>;
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d-cache-size = <0x10000>;
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d-cache-line-size = <0x40>;
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d-cache-sets = <0x100>;
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};
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cpu6: cpu@60000 {
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device_type = "cpu";
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compatible = "arm,neoverse-v3";
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reg = <0x0 0x60000>;
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enable-method = "psci";
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i-cache-size = <0x10000>;
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i-cache-line-size = <0x40>;
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i-cache-sets = <0x100>;
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d-cache-size = <0x10000>;
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d-cache-line-size = <0x40>;
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d-cache-sets = <0x100>;
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};
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cpu7: cpu@70000 {
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device_type = "cpu";
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compatible = "arm,neoverse-v3";
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reg = <0x0 0x70000>;
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enable-method = "psci";
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i-cache-size = <0x10000>;
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i-cache-line-size = <0x40>;
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i-cache-sets = <0x100>;
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d-cache-size = <0x10000>;
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d-cache-line-size = <0x40>;
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d-cache-sets = <0x100>;
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};
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cpu8: cpu@80000 {
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device_type = "cpu";
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compatible = "arm,neoverse-v3";
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reg = <0x0 0x80000>;
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enable-method = "psci";
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i-cache-size = <0x10000>;
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i-cache-line-size = <0x40>;
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i-cache-sets = <0x100>;
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d-cache-size = <0x10000>;
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d-cache-line-size = <0x40>;
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d-cache-sets = <0x100>;
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};
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cpu9: cpu@90000 {
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device_type = "cpu";
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compatible = "arm,neoverse-v3";
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reg = <0x0 0x90000>;
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enable-method = "psci";
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i-cache-size = <0x10000>;
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i-cache-line-size = <0x40>;
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i-cache-sets = <0x100>;
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d-cache-size = <0x10000>;
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d-cache-line-size = <0x40>;
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d-cache-sets = <0x100>;
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};
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cpu10: cpu@a0000 {
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device_type = "cpu";
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compatible = "arm,neoverse-v3";
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reg = <0x0 0xa0000>;
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enable-method = "psci";
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i-cache-size = <0x10000>;
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i-cache-line-size = <0x40>;
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i-cache-sets = <0x100>;
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d-cache-size = <0x10000>;
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d-cache-line-size = <0x40>;
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d-cache-sets = <0x100>;
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};
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cpu11: cpu@b0000 {
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device_type = "cpu";
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compatible = "arm,neoverse-v3";
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reg = <0x0 0xb0000>;
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enable-method = "psci";
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i-cache-size = <0x10000>;
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i-cache-line-size = <0x40>;
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i-cache-sets = <0x100>;
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d-cache-size = <0x10000>;
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d-cache-line-size = <0x40>;
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d-cache-sets = <0x100>;
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};
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cpu12: cpu@c0000 {
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device_type = "cpu";
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compatible = "arm,neoverse-v3";
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reg = <0x0 0xc0000>;
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enable-method = "psci";
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i-cache-size = <0x10000>;
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i-cache-line-size = <0x40>;
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i-cache-sets = <0x100>;
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d-cache-size = <0x10000>;
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d-cache-line-size = <0x40>;
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d-cache-sets = <0x100>;
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};
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cpu13: cpu@d0000 {
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device_type = "cpu";
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compatible = "arm,neoverse-v3";
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reg = <0x0 0xd0000>;
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enable-method = "psci";
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i-cache-size = <0x10000>;
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i-cache-line-size = <0x40>;
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i-cache-sets = <0x100>;
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d-cache-size = <0x10000>;
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d-cache-line-size = <0x40>;
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d-cache-sets = <0x100>;
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};
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cpu14: cpu@e0000 {
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device_type = "cpu";
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compatible = "arm,neoverse-v3";
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reg = <0x0 0xe0000>;
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enable-method = "psci";
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i-cache-size = <0x10000>;
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i-cache-line-size = <0x40>;
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i-cache-sets = <0x100>;
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d-cache-size = <0x10000>;
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d-cache-line-size = <0x40>;
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d-cache-sets = <0x100>;
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};
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cpu15: cpu@f0000 {
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device_type = "cpu";
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compatible = "arm,neoverse-v3";
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reg = <0x0 0xf0000>;
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enable-method = "psci";
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i-cache-size = <0x10000>;
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i-cache-line-size = <0x40>;
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i-cache-sets = <0x100>;
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d-cache-size = <0x10000>;
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d-cache-line-size = <0x40>;
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d-cache-sets = <0x100>;
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};
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};
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memory@80000000 {
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device_type = "memory";
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/*
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* 0x7fc0 0000 - 0x7fff ffff : BL32
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* 0x7fbf 0000 - 0x7fbf ffff : FFA_SHARED_MM_BUF
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*/
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reg = <0x00000000 0x80000000 0 0x7fbf0000>,
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<0x00000080 0x80000000 0 0x80000000>;
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};
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timer {
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compatible = "arm,armv8-timer";
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interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
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<GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
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<GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
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<GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
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};
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soc_clk24mhz: clk24mhz {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <24000000>;
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clock-output-names = "refclk24mhz";
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};
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soc_refclk1mhz: refclk1mhz {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <1000000>;
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clock-output-names = "refclk1mhz";
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};
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soc {
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compatible = "simple-bus";
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#address-cells = <2>;
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#size-cells = <2>;
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ranges;
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gic: interrupt-controller@30000000 {
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compatible = "arm,gic-v3";
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reg = <0x0 0x30000000 0 0x10000>, // GICD
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<0x0 0x301c0000 0 0x8000000>; // GICR
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#interrupt-cells = <3>;
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#address-cells = <2>;
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#size-cells = <2>;
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ranges;
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interrupt-controller;
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interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
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its1: msi-controller@30040000 {
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compatible = "arm,gic-v3-its";
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reg = <0x0 0x30040000 0x0 0x40000>;
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msi-controller;
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#msi-cells = <1>;
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};
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its2: msi-controller@30080000 {
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compatible = "arm,gic-v3-its";
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reg = <0x0 0x30080000 0x0 0x40000>;
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msi-controller;
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#msi-cells = <1>;
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};
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its3: msi-controller@300c0000 {
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compatible = "arm,gic-v3-its";
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reg = <0x0 0x300c0000 0x0 0x40000>;
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msi-controller;
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#msi-cells = <1>;
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};
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its4: msi-controller@30100000 {
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compatible = "arm,gic-v3-its";
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reg = <0x0 0x30100000 0x0 0x40000>;
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msi-controller;
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#msi-cells = <1>;
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};
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its5: msi-controller@30140000 {
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compatible = "arm,gic-v3-its";
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reg = <0x0 0x30140000 0x0 0x40000>;
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msi-controller;
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#msi-cells = <1>;
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};
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its6: msi-controller@30180000 {
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compatible = "arm,gic-v3-its";
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reg = <0x0 0x30180000 0x0 0x40000>;
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msi-controller;
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#msi-cells = <1>;
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};
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};
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soc_serial0: serial@2a400000 {
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compatible = "arm,pl011", "arm,primecell";
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reg = <0x0 0x2a400000 0x0 0x10000>;
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interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&soc_clk24mhz>, <&soc_clk24mhz>;
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clock-names = "uartclk", "apb_pclk";
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};
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watchdog@2a440000 {
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compatible = "arm,sbsa-gwdt";
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reg = <0x0 0x2a440000 0 0x1000>,
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<0x0 0x2a450000 0 0x1000>;
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interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
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};
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rtc@c170000 {
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compatible = "arm,pl031", "arm,primecell";
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reg = <0x0 0x0c170000 0x0 0x10000>;
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interrupts = <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&soc_clk24mhz>;
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clock-names = "apb_pclk";
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};
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virtio-net@c150000 {
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compatible = "virtio,mmio";
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reg = <0x0 0xc150000 0x0 0x200>;
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interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
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};
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virtio-block@c130000 {
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compatible = "virtio,mmio";
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reg = <0x0 0xc130000 0x0 0x200>;
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interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>;
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};
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virtio-rng@c140000 {
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compatible = "virtio,mmio";
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reg = <0x0 0xc140000 0x0 0x200>;
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interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>;
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};
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pci@4000000000 {
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#address-cells = <0x03>;
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#size-cells = <0x02>;
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compatible = "pci-host-ecam-generic";
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device_type = "pci";
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bus-range = <0x00 0x11>;
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reg = <0x40 0x00 0x00 0x04000000>;
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ranges = <0x43000000 0x40 0x40000000 0x40 0x40000000 0x10 0x00000000
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0x02000000 0x00 0x60000000 0x00 0x60000000 0x00 0x08000000
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0x01000000 0x00 0x00 0x00 0x77800000 0x00 0x800000>;
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msi-map = <0x00 &its1 0x40000 0x10000>;
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iommu-map = <0x00 &smmu 0x40000 0x10000>;
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dma-coherent;
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};
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smmu: iommu@280000000 {
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compatible = "arm,smmu-v3";
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reg = <0x2 0x80000000 0x0 0x100000>;
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dma-coherent;
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#iommu-cells = <1>;
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interrupts = <1 210 1>,
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<1 211 1>,
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<1 212 1>,
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<1 213 1>;
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interrupt-names = "eventq", "priq", "cmdq-sync", "gerror";
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msi-parent = <&its1 0x10000>;
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};
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sysreg: sysreg@c010000 {
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compatible = "arm,vexpress-sysreg";
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reg = <0x0 0xc010000 0x0 0x1000>;
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gpio-controller;
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#gpio-cells = <2>;
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};
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fixed_3v3: v2m-3v3@c011000 {
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compatible = "regulator-fixed";
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reg = <0x0 0xc011000 0x0 0x1000>;
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regulator-name = "3V3";
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regulator-min-microvolt = <3300000>;
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regulator-max-microvolt = <3300000>;
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regulator-always-on;
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};
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mmci@c050000 {
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compatible = "arm,pl180", "arm,primecell";
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reg = <0x0 0xc050000 0x0 0x1000>;
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interrupts = <0 0x8B 0x4>,
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<0 0x8C 0x4>;
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cd-gpios = <&sysreg 0 0>;
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wp-gpios = <&sysreg 1 0>;
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bus-width = <8>;
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max-frequency = <12000000>;
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vmmc-supply = <&fixed_3v3>;
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clocks = <&soc_clk24mhz>, <&soc_clk24mhz>;
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clock-names = "mclk", "apb_pclk";
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};
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};
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psci {
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compatible = "arm,psci-1.0", "arm,psci-0.2", "arm,psci";
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method = "smc";
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cpu_suspend = <0xc4000001>;
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cpu_off = <0x84000002>;
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cpu_on = <0x84000003>;
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};
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};
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@ -0,0 +1,21 @@
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/*
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* Copyright (c) 2024, Arm Limited. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <common/tbbr/tbbr_img_def.h>
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/dts-v1/;
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/ {
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dtb-registry {
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compatible = "fconf,dyn_cfg-dtb_registry";
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hw-config {
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load-address = <0x0 0x83000000>;
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max-size = <0x8000>;
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id = <HW_CONFIG_ID>;
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};
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};
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};
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@ -105,6 +105,9 @@
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#define PLAT_ARM_FLASH_IMAGE_BASE V2M_FLASH0_BASE
|
||||
#define PLAT_ARM_FLASH_IMAGE_MAX_SIZE (V2M_FLASH0_SIZE - V2M_FLASH_BLOCK_SIZE)
|
||||
|
||||
#define PLAT_FW_CONFIG_MAX_SIZE (ARM_FW_CONFIG_LIMIT - ARM_FW_CONFIG_BASE)
|
||||
#define PLAT_FW_CONFIG_BASE ARM_FW_CONFIG_BASE
|
||||
|
||||
/* RD1AE-specific memory mappings */
|
||||
#define RD1AE_EXTERNAL_FLASH MAP_REGION_FLAT(V2M_FLASH0_BASE, \
|
||||
V2M_FLASH0_SIZE, \
|
||||
|
|
|
|||
|
|
@ -10,6 +10,7 @@ RD1AE_BASE = plat/arm/board/automotive_rd/platform/rd1ae
|
|||
|
||||
PLAT_INCLUDES += -I${RD1AE_BASE}/include/
|
||||
|
||||
override ARM_FW_CONFIG_LOAD_ENABLE := 1
|
||||
override ARM_PLAT_MT := 1
|
||||
override ARM_RECOM_STATE_ID_ENC := 1
|
||||
override CSS_LOAD_SCP_IMAGES := 0
|
||||
|
|
@ -45,6 +46,18 @@ BL2_SOURCES += ${RD1AE_CPU_SOURCES} \
|
|||
plat/arm/common/arm_nor_psci_mem_protect.c \
|
||||
drivers/arm/sbsa/sbsa.c
|
||||
|
||||
# Add the FDT_SOURCES and options for Dynamic Config
|
||||
FDT_SOURCES += ${RD1AE_BASE}/fdts/${PLAT}_fw_config.dts \
|
||||
fdts/${PLAT}.dts
|
||||
|
||||
FW_CONFIG := ${BUILD_PLAT}/fdts/${PLAT}_fw_config.dtb
|
||||
HW_CONFIG := ${BUILD_PLAT}/fdts/${PLAT}.dtb
|
||||
|
||||
# Add the FW_CONFIG to FIP and specify the same to certtool
|
||||
$(eval $(call TOOL_ADD_PAYLOAD,${FW_CONFIG},--fw-config,${FW_CONFIG}))
|
||||
# Add the HW_CONFIG to FIP and specify the same to certtool
|
||||
$(eval $(call TOOL_ADD_PAYLOAD,${HW_CONFIG},--hw-config,${HW_CONFIG}))
|
||||
|
||||
include plat/arm/common/arm_common.mk
|
||||
include plat/arm/css/common/css_common.mk
|
||||
include plat/arm/board/common/board_common.mk
|
||||
|
|
|
|||
Loading…
Add table
Reference in a new issue