* changes:
refactor(tc): move SCMI nodes into the 'firmware' node
refactor(tc): move MHUv2 property to tc2.dts
refactor(tc): drop the 'mhu-protocol' property in DT binding
refactor(tc): append properties in DT bindings
refactor(tc): move SCMI clock DT binding into tc-base.dtsi
refactor(tc): introduce a new file tc-fpga.dtsi
refactor(tc): move out platform specific DT binding from tc-base.dtsi
refactor(tc): move out platform specific code from tc_vers.dtsi
refactor(tc): add platform specific DT files
refactor(tc): rename 'tc_fvp.dtsi' to 'tc-fvp.dtsi'
refactor(tc): introduce a new macro ADDRESSIFY()
In the ARM recommended StateID Encoding, the index for the power
level where the calling core is last to go idle use the last niblle
of the StateId.
Even if this nibble is necessary for OS-initiated mode, it can be
used by caller even when this OSI mode is not used.
In arm_validate_power_state() function, the StateId is compared with
content of arm_pm_idle_states[] build with the arm_make_pwrstate_lvl2
macro, without Last in Level information. So it is safe to mask this
nibble for ARM platform in all the cases, and that avoids issues with
caller with use the same StateId encoding with OSI mode activated or
not (in tftf tests for example, the input(power state) parameter =
(0x40001022) and the associated power state is 0x40000022).
Change-Id: I45e8e2b8f526fb61b94cf134d7d4aa3bac4c215d
Signed-off-by: Jayanth Dodderi Chidanand <jayanthdodderi.chidanand@arm.com>
Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
* changes:
build: improve diagnostics for unrecognized toolchain tools
build(rzg): separate BL2 and BL31 SREC generation
build(rcar): separate BL2 and BL31 SREC generation
build: separate preprocessing from DTB compilation
build: remove `MAKE_BUILD_STRINGS` function
Move pmf support to vendor-specific EL3 Monitor Service Calls. Remove
pmf call count as it's not supported in vendor-specific el3 as per
SMCCC Documentation 1.5:
https://developer.arm.com/documentation/den0028/latest
Add a deprecation notice to inform PMF is moved from arm-sip range to
vendor-specific EL3 range. PMF support from arm-sip range will be
removed and will not available after TF-A 2.12 release.
Change-Id: Ie1e14aa601d4fc3db352cd5621d842017a18e9ec
Signed-off-by: Govindraj Raja <govindraj.raja@arm.com>
Move debugfs to Vendor-Specific EL3 Monitor Service Calls.
Function Identifier for Vendor-Specific EL3 Monitor Service is '7' and
allocated subranges of Function identifiers to different services are:
0x87000000-0x8700FFFF-SMC32: Vendor-Specific EL3 Monitor Service Calls
0xC7000000-0xC700FFFF-SMC64: Vendor-Specific EL3 Monitor Service Calls
Amend Debugfs FID's to use this range and id.
Add a deprecation notice to inform debugfs moved from arm-sip range to
Vendor-Specific EL3 range. Debugfs support from arm-sip range will be
removed and will not be available after TF-A 2.12 release.
Reference to debugfs component level documentation:
https://trustedfirmware-a.readthedocs.io/en/latest/components/debugfs-design.html#overview
Change-Id: I97a50170178f361f70c95ed0049bc4e278de59d7
Signed-off-by: Govindraj Raja <govindraj.raja@arm.com>
Move CPUs which are not tested in CI under a new build option.
We have added some CPUs for which there is no FVP models available
yet to test. Move those CPUs under a new FVP build option.
Change-Id: I3da12d2f8d9c246b435b31adfac61c79dc1ab0cb
Signed-off-by: Govindraj Raja <govindraj.raja@arm.com>
In this patch, we are trying to introduce the wrapper macro
CREATE_FEATURE_PRESENT to get the following capability and
align it for all the features:
-> is_feat_xx_present(): Does Hardware implement the feature.
-> uniformity in naming the function across multiple features.
-> improved readability
The is_feat_xx_present() is implemented to check if the hardware
implements the feature and does not take into account the
ENABLE_FEAT_XXX flag enabled/disabled in software.
- CREATE_FEATURE_PRESENT(name, idreg, shift, mask, idval)
The wrapper macro reduces the function to a single line and
creates the is_feat_xx_present function that checks the
id register based on the shift and mask values and compares
this against a determined idvalue.
Change-Id: I7b91d2c9c6fbe55f94c693aa1b2c50be54fb9ecc
Signed-off-by: Sona Mathew <sonarebecca.mathew@arm.com>
commit@138221c2457b9d04101b84084c07d576b0eb5a51 reduced items that
should be build due to SRAM size limitations.
But newer models from 11.19 onwards support to set SRAM size greater
than 256KB. So remove all dependency and conditional builds for FVP.
Change-Id: I38684e100450b74fdda0d685775e2cbce92170b6
Signed-off-by: Govindraj Raja <govindraj.raja@arm.com>
Currently, the DT binding uses the file 'tc.dts' as a central place for
all TC platforms. And the variables (for different platforms, or FVP vs
FPGA, etc.) are maintained in 'tc_vers.dtsi'.
This patch renames 'tc.dts' to 'tc-base.dtsi' and creates an individual
.dts file for every platform. The purpose is to use 'tc-base.dtsi' for
maintaining common DT binding and every platform's specific definitions
will be moved into its own .dts file. This is a preparation for
sequential refactoring.
It changes to include the header files in platform DTS files but not in
the 'tc-base.dtsi'. This can allow 'tc-base.dtsi' is general enough and
platform DTS files covers platform specific defintions.
Change-Id: I034fb3f8836bcea36e8ad8ae01de41127693b0c6
Signed-off-by: Leo Yan <leo.yan@arm.com>
Commit c282384db ("refactor(mte): remove mte, mte_perm") removes the
option FEAT_MTE and introduces FEAT_MTE2 option. Afterwards, the
FEAT_MTE2 option is missed on the TC platform and the feature is
disabled. As a result, it causes the panic in secure world.
This patch enables the FEAT_MTE2 option for TC platform to allow the
secure world can access the MTE registers properly.
Change-Id: If697236aa59bf4fb374e0ff43b53455ac2154e9c
Fixes: c282384db ("refactor(mte): remove mte, mte_perm")
Signed-off-by: Leo Yan <leo.yan@arm.com>
This function causes the build message to be generated and compiled in
two different ways, with one way done inside `build_macros.mk` and the
other done inside `windows.mk`, mostly because it's done by generating
the C file on the command line.
We can instead replace this whole build message generation sequence with
a simple standard C compilation command and a normal C file.
Change-Id: I8bc136380c9585ddeec9a11154ee39ef70526f81
Signed-off-by: Chris Kay <chris.kay@arm.com>
The stack is too small for VERBOSE logging when secure world is disabled
as there is a recursive call when printing the translation table state
which causes a crash.
Changing the stack to the same value regardless of trusted boot.
Change-Id: I12298b33e47ae5206f74370262edce06b8a75d99
Signed-off-by: Alex Dobrescu <alex.dobrescu@arm.com>
Signed-off-by: Leo Yan <leo.yan@arm.com>
* changes:
refactor(changelog): change all occurrences of RSS to RSE
refactor(qemu): change all occurrences of RSS to RSE
refactor(fvp): change all occurrences of RSS to RSE
refactor(fiptool): change all occurrences of RSS to RSE
refactor(psa): change all occurrences of RSS to RSE
refactor(fvp): remove leftovers from rss measured boot support
refactor(tc): change all occurrences of RSS to RSE
docs: change all occurrences of RSS to RSE
refactor(measured-boot): change all occurrences of RSS to RSE
refactor(rse): change all occurrences of RSS to RSE
refactor(psa): rename all 'rss' files to 'rse'
refactor(tc): rename all 'rss' files to 'rse'
docs: rename all 'rss' files to 'rse'
refactor(measured-boot): rename all 'rss' files to 'rse'
refactor(rss): rename all 'rss' files to 'rse'
When BL2 is enabled as the entrypoint in the reset vector, none of the
TL initialisation ordinarily performed in BL1 will have been done. This
change ensures that BL2 has a secure TL to pass information onto BL31
through.
Change-Id: I553b0b7aac9390cd6a2d63471b81ddc72cc40a60
Signed-off-by: Harrison Mutai <harrison.mutai@arm.com>
Leverage the framework between BL1 and BL2. Migrate all handoff
structures to the TL.
Change-Id: I79ff3a319596b5656184cde10b5204b10a4d03bb
Signed-off-by: Harrison Mutai <harrison.mutai@arm.com>
Layout calculation is spread out between core BL1 logic and common
platform code. Relocate these into common platform code so they are
organised logically.
Change-Id: I8b05403e41b800957a0367316cecd373d10bb1a4
Signed-off-by: Harrison Mutai <harrison.mutai@arm.com>
Add support for the firmware handoff framework between BL2 and BL31.
Create a transfer list in trusted SRAM, leveraging the larger SRAM sizes
in recent models. Load the HW_CONFIG as a TE along with entry point
parameters for BL31 execution.
Change-Id: I7c4c6e8353ca978a13520fb3e15fb2803f0f1d0e
Signed-off-by: Harrison Mutai <harrison.mutai@arm.com>
The soc_css.mk file within the plat/arm/soc module currently implements
initialization functions for the PCIe controller and NIC400 within the
SOC specification. However, as none of the Neoverse reference design
platforms necessitate the initialization of PCIe or NIC400, remove the
soc_css.mk from the common makefile.
Additionally, empty initialization functions for PCIe and NIC400 are
added to satisfy the requirements of the plat/arm common code, which
expects these functions to be present.
Signed-off-by: Rohit Mathew <Rohit.Mathew@arm.com>
Change-Id: Ia431af62f48fc224962d64902dd3acfbf0b93935
The existing macros representing GIC SPI minimum and maximum for
multichip platforms lack a consistent naming convention. To address
this, establish the convention "NRD_CHIP<x>_SPI_MIN" and
"NRD_CHIP<x>_SPI_MAX" for use across all Neoverse Reference Design
multichip platforms.
Furthermore, extend this naming convention to RD-N2-Cfg2 and introduce
similar macros.
Signed-off-by: Rohit Mathew <rohit.mathew@arm.com>
Change-Id: Idca2a8c66579f05e712e3b6e95204fedc122cf23
Consolidate and organize platform port definitions within the
nrd_plat_arm_def2.h file. Remove direct references to addresses with
corresponding RoS or CSS definitions.
Signed-off-by: Rohit Mathew <rohit.mathew@arm.com>
Change-Id: Ic43cff90d2cf45760b3f808732754cf7c05a814a
SPMD_SPM_AT_SEL2 is enabled by default for platforms. As the platforms
based on N2/V2 CPUs don't use SPMD_SPM_AT_SEL2, set its value to 0.
Signed-off-by: Rohit Mathew <rohit.mathew@arm.com>
Change-Id: Ib503c5552e2b8fee928b2392ba40805664d857d7
Set build-option ENABLE_FEAT_AMU to 2 so that AMU is enabled if the
feature is implemented on the platform. This would ensure that lower ELs
could access system registers relevant to AMU without causing a trap to
EL3.
Signed-off-by: Rohit Mathew <rohit.mathew@arm.com>
Change-Id: Ic9aa435af54eddacdaa49e69f25893ddaa977e3e
MTE2 is an optional feature that could be part of platforms based on Arm
V8.5 or above. If this feature is implemented on the platform, lower ELs
could potentially access the featre registers leading EL3 traps.
Therefore, set MTE2 build option to '2' to enable the feature only if
its implemented on the platform.
Signed-off-by: Rohit Mathew <rohit.mathew@arm.com>
Change-Id: I97c341ac38485937eb18ce9bdcffec26c0e5e76d
Presently, the second generation platforms have direct references to CSS
and ROS specific addresses within RD-N2's platform header file
(platform_def.h). Moreover, there are platform port specific macros
defined within platform_def.h To enhance organization and
appropriateness, relocate these definitions to nrd_css_def2.h,
nrd_ros_def2.h and nrd_arm_platform_def1.h files accordingly. Reuse
these definitions within the platform_def.h files as needed.
Additionally, remove reference to the unused PLAT_ARM_GICC_BASE macro
from the individual platform_def.h file.
Signed-off-by: Rohit Mathew <rohit.mathew@arm.com>
Change-Id: I9a237c3ae28d7e209188e2c37c8494b4a420ee83
In the current setup, the base and size of the ROM, SRAM, and DRAM2
regions are directly defined in the nrd_fw_def2.h file for N2 CPU based
platforms. To enhance modularity and appropriateness, introduce macros
for these definitions in the respective css file (nrd_css_def2.h). While
the maximum sizes for ROM, SRAM, and DRAM2 are specified in the css
specification, the actual implementation sizes may vary. Consequently,
relocate the size macros to the platform-specific platform_def.h file
for individual platforms.
Signed-off-by: Rohit Mathew <rohit.mathew@arm.com>
Change-Id: I30988bf63cf942f68188a70697cc43cb6af96a9c
As part of the refactoring for the second generation platforms,
introduce a naming convention for macros within nrd_ros_def2.h and
nrd_ros_fw_def2.h. All macros, except those related to page table
entries, must adhere to the format NRD_ROS_<name>. Page table entry
macros are handled separately and are not part of this patch.
Signed-off-by: Rohit Mathew <rohit.mathew@arm.com>
Change-Id: Ifcdc30b1c80b9848b793de2013095fc98d57bec6
As part of the refactoring for the second generation of platforms,
introduce a naming convention for macros within nrd_css_def2.h and
nrd_css_fw_def2.h. All macros, except those related to page table
entries, must adhere to the format NRD_CSS_<name>. Page table entry
macros are handled separately and are not part of this patch.
Signed-off-by: Rohit Mathew <rohit.mathew@arm.com>
Change-Id: Ib168320e12f06cd034342c011909896de463ab27
There are two macros that define ROS device memory map range and
attributes - one for local chip and the other for remote chip. Refactor
these two macros into a single macro that uses the chip ID to identify
the local or the remote chip.
Signed-off-by: Rohit Mathew <rohit.mathew@arm.com>
Change-Id: I58eb65c2f046b6074f848f1448cd10a7dcc37f74
There are two macros that define CSS device memory map range and
attributes - one for local chip and the other for remote chip. Refactor
these two macros into a single macro that uses the chip ID to identify
the local or the remote chip. While at it, rename the macro that defines
the memory map range and attributes for the remote shared RAM region.
Signed-off-by: Rohit Mathew <rohit.mathew@arm.com>
Change-Id: Ieddd5c81f6261490dbacb97160858903e56d327a
Presently, for the second generation platforms based on the N2 CPU,
macros related to page table entries lack a consistent naming
convention. This absence may lead to potential mix-ups, such as css
definitions in soc files, and can contribute to decreased code clarity.
To address this, establish the following naming convention:
- NRD_CSS_<name>_MMAP for CSS related page table entries
- NRD_ROS_<name>_MMAP for ROS related page table entries
Signed-off-by: Rohit Mathew <rohit.mathew@arm.com>
Change-Id: I7bf1f9b0ddfd0444c802a23143de6a163f127731
Header files for N2 CPU based platforms currently use "2" as
a suffix. Rename the common source file, nrd_plat_v2.c used by these
platforms to nrd_plat2.c to align with this convention.
Signed-off-by: Rohit Mathew <rohit.mathew@arm.com>
Change-Id: I36b138a0a4dff8087e52f0f2cbc21abc03a793ad
Continuing the refactoring of the various definition for platforms based
on N2/V2 CPU, refactor the definitions in the nrd_soc_css_def_v2.h file
into the following files as appropriate.
- nrd_ros_def2.h: includes RoS hardware related definitions
- nrd_plat_arm_def2.h: includes platform port related definitions
Signed-off-by: Rohit Mathew <rohit.mathew@arm.com>
Change-Id: Ib447e67a0a42722735297b27b7f5017bc146156c
Continuing the refactoring of the various definitions for the second
generation platforms based on the N2/V2 CPU, refactor the definitions in
the nrd_soc_platform_def_v2.h file into the following files as
appropriate.
- nrd_ros_def2.h: includes RoS hardware related definitions
- nrd_ros_fw_def2.h: includes RoS firmware related definitions
- nrd_plat_arm_def2.h: includes platform port related definitions
RoS (Rest Of System) is used to refer to the part of the reference
design platform that excludes CSS. The file inclusions in the
platform_def.h file of the platforms have been updated accordingly.
Signed-off-by: Rohit Mathew <rohit.mathew@arm.com>
Change-Id: I393e6f4a84be45f1781ea281bd55fa813803f6db
The nrd_base_platform_def.h file includes CSS, RoS, firmware and
platform port related definitions. This approach of consolidating the
various definitions for multiple generation of platforms into the
nrd_base_platform_def.h file is not scaling well.
So in preparation of moving away from the use of nrd_base_platform_def.h
file for the second generation platforms based on N2/V2 CPUs, split the
definitions in this file into multiple include files. The new files into
which the definitions are refactored are -
- nrd_css_def2.h: includes CSS hardware related definitions
- nrd_css_fw_def2.h: includes CSS firmware related definitions
- nrd_ros_fw_def2.h: includes RoS firmware related definitions
- nrd_plat_arm_def2.h: includes platform port elated definitions
RoS (Rest Of System) is used to refer to the part of the reference
design platform that excludes CSS. The definitions that are only
relavant to the aforementioned platforms have been refactored from the
nrd_base_platform_def.h file.
Signed-off-by: Rohit Mathew <rohit.mathew@arm.com>
Change-Id: I45f680857328fa77f0977897490b225bdb29efe4
Presently, platforms such as RD-N2, RD-N2-Cfg1, RD-N2-Cfg2 and RD-V2
utilize nrd_soc_platform_def_v2.h and nrd_soc_css_def_v2.h for all css
and soc-related defines. So move these two header files into a new
directory named 'nrd2'. This new directory will serve as the container
of header files that are specific to the former stated platforms.
Signed-off-by: Rohit Mathew <rohit.mathew@arm.com>
Change-Id: I51ba0944dea91ae81e1840947d2e9af9b28d561d
As RD-N1-Edge is not planned to be deprecated in the upcoming release
cycles, remove it from the deprecated list.
Change-Id: I6af06e7bd162747aab72384185951d218b388ed3
Signed-off-by: Rohit Mathew <rohit.mathew@arm.com>
As SGI-575 is not planned to be deprecated in the upcoming release
cycles, remove it from the deprecated list.
Change-Id: Ic9171a3e1bec198d9305e75ac5cae4b40498537e
Signed-off-by: Rohit Mathew <rohit.mathew@arm.com>
SPMD_SPM_AT_SEL2 is enabled by default for platforms. As the platforms
based on A75/V1/N1 CPUs don't use SPMD_SPM_AT_SEL2, set its value to 0.
Signed-off-by: Rohit Mathew <rohit.mathew@arm.com>
Change-Id: I59703ddd769f61778ea06cc183e1b163369281f1
Set build-option ENABLE_FEAT_AMU to 2 for RD-V1 and RD-V1-MC so that AMU
is enabled if the feature is implemented on these platforms. This would
ensure that lower ELs could access system registers relevant to AMU
without causing a trap to EL3.
Signed-off-by: Rohit Mathew <rohit.mathew@arm.com>
Change-Id: I4d34db0c102c786f34103746064e22600d28da33
As the last step of refactoring the platform support of the first
generation of reference design platforms (A75/N1/V1), clean-up the
platform port definitions listed in the nrd_plat_arm_def1.h file.
Signed-off-by: Rohit Mathew <rohit.mathew@arm.com>
Change-Id: I73a9b94f1db22192398ea8211109d2e4aaf965e1
As part of the refactoring for A75/V1/N1 CPU based platforms, remove
unused defines from the platform_def.h for each of these platforms.
Signed-off-by: Rohit Mathew <rohit.mathew@arm.com>
Change-Id: I37a6d82ad2f80a5c92b2652432fe2d211e052580
Presently, A75/V1/N1 CPU based platforms have platform port specific
macros defined within their platform_def.h file. To enhance organization
and appropriateness, relocate these definitions to
nrd_arm_platform_def1.h.
Signed-off-by: Rohit Mathew <rohit.mathew@arm.com>
Change-Id: I1f55192185df1509756bc2ef022e5aed0724dd05
