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refactor(neoverse-rd): define naming convention for CSS macros

Browse source 
As part of the refactoring for the second generation of platforms,
introduce a naming convention for macros within nrd_css_def2.h and
nrd_css_fw_def2.h. All macros, except those related to page table
entries, must adhere to the format NRD_CSS_<name>. Page table entry
macros are handled separately and are not part of this patch.

Signed-off-by: Rohit Mathew <rohit.mathew@arm.com>
Change-Id: Ib168320e12f06cd034342c011909896de463ab27
This commit is contained in:
Rohit Mathew 2024-03-18 19:16:37 +00:00
parent 37f59e4ea4
commit 069bad718f
7 changed files with 41 additions and 40 deletions
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14
plat/arm/board/neoverse_rd/common/include/nrd2/nrd_css_def2.h
View file

@ -15,18 +15,18 @@
******************************************************************************/
/* PL011 UART */
#define SOC_CSS_SEC_UART_BASE UL(0x2A410000)
#define SOC_CSS_NSEC_UART_BASE UL(0x2A400000)
#define SOC_CSS_UART_SIZE UL(0x10000)
#define NRD_CSS_SEC_UART_BASE UL(0x2A410000)
#define NRD_CSS_NSEC_UART_BASE UL(0x2A400000)
#define NRD_CSS_UART_SIZE UL(0x10000)
/* General Peripherals */
#define NRD_DEVICE_BASE UL(0x20000000)
#define NRD_DEVICE_SIZE UL(0x20000000)
#define NRD_CSS_PERIPH_BASE UL(0x20000000)
#define NRD_CSS_PERIPH_SIZE UL(0x20000000)
/* NS RAM Error record */
#define SOC_NS_RAM_ERR_REC_BASE UL(0x2A4C0000)
#define NRD_CSS_NS_RAM_ERR_REC_BASE UL(0x2A4C0000)
/*Secure Watchdog */
#define SBSA_SECURE_WDOG_BASE UL(0x2A480000)
#define NRD_CSS_SECURE_WDOG_BASE UL(0x2A480000)
#endif /* NRD_CSS_DEF2_H */

28
plat/arm/board/neoverse_rd/common/include/nrd2/nrd_css_fw_def2.h
View file

@ -24,26 +24,26 @@
* A buffer of ~35KB is added to account for future expansion of the image,
* making it a total of 100KB.
*/
#define NRD_BL31_SIZE UL(116 * 1024) /* 116 KB */
#define NRD_CSS_BL31_SIZE UL(116 * 1024) /* 116 KB */
/*******************************************************************************
* Console config
******************************************************************************/
#define SOC_CSS_UART_CLK_IN_HZ UL(7372800)
#define NRD_CSS_UART_CLK_IN_HZ UL(7372800)
/*******************************************************************************
* Watchdog config
******************************************************************************/
#define SBSA_SECURE_WDOG_TIMEOUT UL(100)
#define NRD_CSS_SECURE_WDOG_TIMEOUT UL(100)
/*******************************************************************************
* RAS config
******************************************************************************/
#define NS_RAM_ECC_CE_INT U(87)
#define NS_RAM_ECC_UE_INT U(88)
#define NRD_CSS_NS_RAM_ECC_CE_INT U(87)
#define NRD_CSS_NS_RAM_ECC_UE_INT U(88)
#if (SPM_MM || (SPMC_AT_EL3 && SPMC_AT_EL3_SEL0_SP)) \
&& ENABLE_FEAT_RAS && FFH_SUPPORT
@ -51,9 +51,9 @@
* CPER buffer memory of 128KB is reserved and it is placed adjacent to the
* memory shared between EL3 and S-EL0.
*/
#define NRD_SP_CPER_BUF_BASE (PLAT_SP_IMAGE_NS_BUF_BASE + \
#define NRD_CSS_SP_CPER_BUF_BASE (PLAT_SP_IMAGE_NS_BUF_BASE + \
PLAT_SP_IMAGE_NS_BUF_SIZE)
#define NRD_SP_CPER_BUF_SIZE UL(0x10000)
#define NRD_CSS_SP_CPER_BUF_SIZE UL(0x10000)
#endif /* SPM_MM && ENABLE_FEAT_RAS && FFH_SUPPORT */
/*******************************************************************************
@ -70,8 +70,8 @@
#define NRD_CSS_PERIPH_MMAP(n) \
MAP_REGION_FLAT( \
NRD_REMOTE_CHIP_MEM_OFFSET(n) + \
NRD_DEVICE_BASE, \
NRD_DEVICE_SIZE, \
NRD_CSS_PERIPH_BASE, \
NRD_CSS_PERIPH_SIZE, \
MT_DEVICE | MT_RW | MT_SECURE)
#if (SPM_MM || (SPMC_AT_EL3 && SPMC_AT_EL3_SEL0_SP)) && \
@ -82,9 +82,9 @@ ENABLE_FEAT_RAS && FFH_SUPPORT
*/
#define NRD_CSS_SP_CPER_BUF_MMAP \
MAP_REGION2( \
NRD_SP_CPER_BUF_BASE, \
NRD_SP_CPER_BUF_BASE, \
NRD_SP_CPER_BUF_SIZE, \
NRD_CSS_SP_CPER_BUF_BASE, \
NRD_CSS_SP_CPER_BUF_BASE, \
NRD_CSS_SP_CPER_BUF_SIZE, \
MT_RW_DATA | MT_NS | MT_USER, \
PAGE_SIZE)
#endif
@ -92,8 +92,8 @@ ENABLE_FEAT_RAS && FFH_SUPPORT
#if SPM_MM
#define NRD_CSS_SECURE_UART_USER_MMAP \
MAP_REGION_FLAT( \
SOC_CSS_SEC_UART_BASE, \
SOC_CSS_UART_SIZE, \
NRD_CSS_SEC_UART_BASE, \
NRD_CSS_UART_SIZE, \
MT_DEVICE | MT_RW | MT_SECURE | MT_USER)
#endif

16
plat/arm/board/neoverse_rd/common/include/nrd2/nrd_plat_arm_def2.h
View file

@ -105,7 +105,7 @@
0x2000))
#endif
#define PLAT_ARM_MAX_BL31_SIZE (NRD_BL31_SIZE + \
#define PLAT_ARM_MAX_BL31_SIZE (NRD_CSS_BL31_SIZE + \
PLAT_ARM_MAX_BL2_SIZE + \
PLAT_ARM_MAX_BL1_RW_SIZE)
@ -145,7 +145,7 @@ ENABLE_FEAT_RAS && FFH_SUPPORT
*/
#define PLAT_ARM_SP_IMAGE_STACK_BASE (PLAT_SP_IMAGE_NS_BUF_BASE + \
PLAT_SP_IMAGE_NS_BUF_SIZE + \
NRD_SP_CPER_BUF_SIZE)
NRD_CSS_SP_CPER_BUF_SIZE)
#elif (SPM_MM || (SPMC_AT_EL3 && SPMC_AT_EL3_SEL0_SP))
/*
* Secure partition stack follows right after the memory region that is shared
@ -159,14 +159,14 @@ ENABLE_FEAT_RAS && FFH_SUPPORT
* Console config
******************************************************************************/
#define PLAT_ARM_BOOT_UART_BASE SOC_CSS_SEC_UART_BASE
#define PLAT_ARM_BOOT_UART_CLK_IN_HZ SOC_CSS_UART_CLK_IN_HZ
#define PLAT_ARM_BOOT_UART_BASE NRD_CSS_SEC_UART_BASE
#define PLAT_ARM_BOOT_UART_CLK_IN_HZ NRD_CSS_UART_CLK_IN_HZ
#define PLAT_ARM_RUN_UART_BASE SOC_CSS_SEC_UART_BASE
#define PLAT_ARM_RUN_UART_CLK_IN_HZ SOC_CSS_UART_CLK_IN_HZ
#define PLAT_ARM_RUN_UART_BASE NRD_CSS_SEC_UART_BASE
#define PLAT_ARM_RUN_UART_CLK_IN_HZ NRD_CSS_UART_CLK_IN_HZ
#define PLAT_ARM_CRASH_UART_BASE SOC_CSS_SEC_UART_BASE
#define PLAT_ARM_CRASH_UART_CLK_IN_HZ SOC_CSS_UART_CLK_IN_HZ
#define PLAT_ARM_CRASH_UART_BASE NRD_CSS_SEC_UART_BASE
#define PLAT_ARM_CRASH_UART_CLK_IN_HZ NRD_CSS_UART_CLK_IN_HZ
/*******************************************************************************
* SCMI config

4
plat/arm/board/neoverse_rd/common/nrd_plat2.c
View file

@ -171,12 +171,12 @@ int plat_get_mbedtls_heap(void **heap_addr, size_t *heap_size)
void plat_arm_secure_wdt_start(void)
{
sbsa_wdog_start(SBSA_SECURE_WDOG_BASE, SBSA_SECURE_WDOG_TIMEOUT);
sbsa_wdog_start(NRD_CSS_SECURE_WDOG_BASE, NRD_CSS_SECURE_WDOG_TIMEOUT);
}
void plat_arm_secure_wdt_stop(void)
{
sbsa_wdog_stop(SBSA_SECURE_WDOG_BASE);
sbsa_wdog_stop(NRD_CSS_SECURE_WDOG_BASE);
}
static sds_region_desc_t nrd_sds_regions[] = {

5
plat/arm/board/neoverse_rd/common/ras/nrd_ras_sram.c
View file

@ -56,8 +56,9 @@ int nrd_ras_sram_intr_handler(const struct err_record_info *err_rec,
/* Determine error record base address to read. */
base_addr = 0;
if (intr == NS_RAM_ECC_CE_INT || intr == NS_RAM_ECC_UE_INT) {
base_addr = SOC_NS_RAM_ERR_REC_BASE;
if (intr == NRD_CSS_NS_RAM_ECC_CE_INT ||
intr == NRD_CSS_NS_RAM_ECC_UE_INT) {
base_addr = NRD_CSS_NS_RAM_ERR_REC_BASE;
}
sram_info.err_status = mmio_read_32(base_addr + ERRSTATUS);
sram_info.err_code = mmio_read_32(base_addr + ERRCODE);

10
plat/arm/board/neoverse_rd/platform/rdn2/rdn2_ras.c
View file

@ -11,10 +11,10 @@
struct nrd_ras_ev_map plat_ras_map[] = {
/* Non Secure base RAM ECC CE interrupt */
{NRD_SDEI_DS_EVENT_0, NS_RAM_ECC_CE_INT, NRD_RAS_INTR_TYPE_SPI},
{NRD_SDEI_DS_EVENT_0, NRD_CSS_NS_RAM_ECC_CE_INT, NRD_RAS_INTR_TYPE_SPI},
/* Non Secure base RAM ECC UE interrupt */
{NRD_SDEI_DS_EVENT_0, NS_RAM_ECC_UE_INT, NRD_RAS_INTR_TYPE_SPI},
{NRD_SDEI_DS_EVENT_0, NRD_CSS_NS_RAM_ECC_UE_INT, NRD_RAS_INTR_TYPE_SPI},
/* CPU 1-bit ECC CE error interrupt */
{NRD_SDEI_DS_EVENT_1, PLAT_CORE_FAULT_IRQ, NRD_RAS_INTR_TYPE_PPI}
@ -23,7 +23,7 @@ struct nrd_ras_ev_map plat_ras_map[] = {
/* RAS error record list definition, used by the common RAS framework. */
struct err_record_info plat_err_records[] = {
/* Base element RAM Non-secure error record. */
ERR_RECORD_MEMMAP_V1(SOC_NS_RAM_ERR_REC_BASE, 4, NULL,
ERR_RECORD_MEMMAP_V1(NRD_CSS_NS_RAM_ERR_REC_BASE, 4, NULL,
&nrd_ras_sram_intr_handler, 0),
ERR_RECORD_SYSREG_V1(0, 1, NULL, &nrd_ras_cpu_intr_handler, 0),
};
@ -34,10 +34,10 @@ struct ras_interrupt plat_ras_interrupts[] = {
.intr_number = PLAT_CORE_FAULT_IRQ,
.err_record = &plat_err_records[1],
}, {
.intr_number = NS_RAM_ECC_CE_INT,
.intr_number = NRD_CSS_NS_RAM_ECC_CE_INT,
.err_record = &plat_err_records[0],
}, {
.intr_number = NS_RAM_ECC_UE_INT,
.intr_number = NRD_CSS_NS_RAM_ECC_UE_INT,
.err_record = &plat_err_records[0],
},
};

4
plat/arm/board/neoverse_rd/platform/rdn2/rdn2_security.c
View file

@ -9,8 +9,8 @@
#include <platform_def.h>
#define RDN2_TZC_CPER_REGION \
{NRD_SP_CPER_BUF_BASE, (NRD_SP_CPER_BUF_BASE + \
NRD_SP_CPER_BUF_SIZE) - 1, TZC_REGION_S_NONE, \
{NRD_CSS_SP_CPER_BUF_BASE, (NRD_CSS_SP_CPER_BUF_BASE + \
NRD_CSS_SP_CPER_BUF_SIZE) - 1, TZC_REGION_S_NONE, \
PLAT_ARM_TZC_NS_DEV_ACCESS}
static const arm_tzc_regions_info_t tzc_regions[] = {