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refactor(neoverse-rd): refactor nrd_soc_platform_def_v2.h file
Continuing the refactoring of the various definitions for the second generation platforms based on the N2/V2 CPU, refactor the definitions in the nrd_soc_platform_def_v2.h file into the following files as appropriate. - nrd_ros_def2.h: includes RoS hardware related definitions - nrd_ros_fw_def2.h: includes RoS firmware related definitions - nrd_plat_arm_def2.h: includes platform port related definitions RoS (Rest Of System) is used to refer to the part of the reference design platform that excludes CSS. The file inclusions in the platform_def.h file of the platforms have been updated accordingly. Signed-off-by: Rohit Mathew <rohit.mathew@arm.com> Change-Id: I393e6f4a84be45f1781ea281bd55fa813803f6db
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6 changed files with 44 additions and 32 deletions
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@ -13,6 +13,7 @@
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#ifndef NRD_PLAT_ARM_DEF2_H
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#define NRD_PLAT_ARM_DEF2_H
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#include <nrd_soc_css_def_v2.h>
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#include <plat/arm/common/arm_def.h>
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#include <plat/arm/common/arm_spm_def.h>
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#include <plat/arm/css/common/css_def.h>
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/*
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* Copyright (c) 2024, Arm Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*
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* This file contains the RoS specific definitions for the second generation
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* platforms based on the N2/V2 CPU.
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*/
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#ifndef NRD_ROS_DEF2_H
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#define NRD_ROS_DEF2_H
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/*******************************************************************************
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* SoC memory map related defines
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******************************************************************************/
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/* System Reg */
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#define CSS_SYSTEMREG_DEVICE_BASE UL(0x0C010000)
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#define CSS_SYSTEMREG_DEVICE_SIZE UL(0x00010000)
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/* NOR flash 2 */
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#define CSS_NOR2_FLASH_DEVICE_BASE ULL(0x001054000000)
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#define CSS_NOR2_FLASH_DEVICE_SIZE UL(0x000004000000)
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/* Memory controller */
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#define SOC_MEMCNTRL_BASE UL(0x10000000)
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#define SOC_MEMCNTRL_SIZE UL(0x10000000)
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#endif /* NRD_ROS_DEF2_H */
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@ -11,6 +11,8 @@
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#ifndef NRD_ROS_FW_DEF2_H
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#define NRD_ROS_FW_DEF2_H
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#include <nrd_ros_def2.h>
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/*******************************************************************************
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* MMU mapping
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******************************************************************************/
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SOC_MEMCNTRL_SIZE, \
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MT_DEVICE | MT_RW | MT_SECURE)
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#define PLAT_ARM_SECURE_MAP_SYSTEMREG \
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MAP_REGION_FLAT( \
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CSS_SYSTEMREG_DEVICE_BASE, \
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CSS_SYSTEMREG_DEVICE_SIZE, \
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MT_DEVICE | MT_RW | MT_SECURE | MT_USER)
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#define PLAT_ARM_SECURE_MAP_NOR2 \
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MAP_REGION_FLAT( \
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CSS_NOR2_FLASH_DEVICE_BASE, \
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CSS_NOR2_FLASH_DEVICE_SIZE, \
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MT_DEVICE | MT_RW | MT_SECURE | MT_USER)
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/*******************************************************************************
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* TZ config
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******************************************************************************/
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@ -1,30 +0,0 @@
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/*
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* Copyright (c) 2020-2024, Arm Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef NRD_SOC_PLATFORM_DEF_V2_H
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#define NRD_SOC_PLATFORM_DEF_V2_H
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#include <nrd_soc_css_def_v2.h>
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/* Map the System registers to access from S-EL0 */
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#define CSS_SYSTEMREG_DEVICE_BASE (0x0C010000)
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#define CSS_SYSTEMREG_DEVICE_SIZE (0x00010000)
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#define PLAT_ARM_SECURE_MAP_SYSTEMREG MAP_REGION_FLAT( \
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CSS_SYSTEMREG_DEVICE_BASE, \
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CSS_SYSTEMREG_DEVICE_SIZE, \
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(MT_DEVICE | MT_RW | \
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MT_SECURE | MT_USER))
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/* Map the NOR2 Flash to access from S-EL0 */
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#define CSS_NOR2_FLASH_DEVICE_BASE (0x001054000000)
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#define CSS_NOR2_FLASH_DEVICE_SIZE (0x000004000000)
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#define PLAT_ARM_SECURE_MAP_NOR2 MAP_REGION_FLAT( \
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CSS_NOR2_FLASH_DEVICE_BASE, \
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CSS_NOR2_FLASH_DEVICE_SIZE, \
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(MT_DEVICE | MT_RW | \
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MT_SECURE | MT_USER))
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#endif /* NRD_SOC_PLATFORM_DEF_V2_H */
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@ -13,7 +13,6 @@
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#include <nrd_plat_arm_def2.h>
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#include <nrd_ros_fw_def2.h>
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#include <nrd_sdei.h>
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#include <nrd_soc_platform_def_v2.h>
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/* Remote chip address offset */
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#define NRD_REMOTE_CHIP_MEM_OFFSET(n) \
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#include <services/el3_spmc_ffa_memory.h>
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#include <nrd_plat.h>
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#include <nrd_soc_platform_def_v2.h>
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#include <rdn2_ras.h>
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#if defined(IMAGE_BL31)
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