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chore: rename hermes to neoverse-n3

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Rename hermes cpu to Neoverse-N3

Change-Id: I912d4c824c5004a8c1909c68fef77f1f5e202b8a
Signed-off-by: Govindraj Raja <govindraj.raja@arm.com>
This commit is contained in:
Govindraj Raja 2024-05-06 12:52:17 -05:00
parent 2a0ca84f47
commit ba6b69494b
3 changed files with 29 additions and 29 deletions
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16
include/lib/cpus/aarch64/neoverse_hermes.h → include/lib/cpus/aarch64/neoverse_n3.h
View file

@ -1,23 +1,23 @@
/*
* Copyright (c) 2023, Arm Limited. All rights reserved.
* Copyright (c) 2023-2024, Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef NEOVERSE_HERMES_H
#define NEOVERSE_HERMES_H
#ifndef NEOVERSE_N3_H
#define NEOVERSE_N3_H
#define NEOVERSE_HERMES_MIDR U(0x410FD8E0)
#define NEOVERSE_N3_MIDR U(0x410FD8E0)
/*******************************************************************************
* CPU Extended Control register specific definitions
******************************************************************************/
#define NEOVERSE_HERMES_CPUECTLR_EL1 S3_0_C15_C1_4
#define NEOVERSE_N3_CPUECTLR_EL1 S3_0_C15_C1_4
/*******************************************************************************
* CPU Power Control register specific definitions
******************************************************************************/
#define NEOVERSE_HERMES_CPUPWRCTLR_EL1 S3_0_C15_C2_7
#define NEOVERSE_HERMES_CPUPWRCTLR_EL1_CORE_PWRDN_BIT U(1)
#define NEOVERSE_N3_CPUPWRCTLR_EL1 S3_0_C15_C2_7
#define NEOVERSE_N3_CPUPWRCTLR_EL1_CORE_PWRDN_BIT U(1)
#endif /* NEOVERSE_HERMES_H */
#endif /* NEOVERSE_N3_H */

40
lib/cpus/aarch64/neoverse_hermes.S → lib/cpus/aarch64/neoverse_n3.S
View file

@ -1,5 +1,5 @@
/*
* Copyright (c) 2023, Arm Limited. All rights reserved.
* Copyright (c) 2023-2024, Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@ -7,43 +7,43 @@
#include <arch.h>
#include <asm_macros.S>
#include <common/bl_common.h>
#include <neoverse_hermes.h>
#include <neoverse_n3.h>
#include <cpu_macros.S>
#include <plat_macros.S>
/* Hardware handled coherency */
#if HW_ASSISTED_COHERENCY == 0
#error "Neoverse Hermes must be compiled with HW_ASSISTED_COHERENCY enabled"
#error "Neoverse-N3 must be compiled with HW_ASSISTED_COHERENCY enabled"
#endif
/* 64-bit only core */
#if CTX_INCLUDE_AARCH32_REGS == 1
#error "Neoverse Hermes supports only AArch64. Compile with CTX_INCLUDE_AARCH32_REGS=0"
#error "Neoverse-N3 supports only AArch64. Compile with CTX_INCLUDE_AARCH32_REGS=0"
#endif
cpu_reset_func_start neoverse_hermes
cpu_reset_func_start neoverse_n3
/* Disable speculative loads */
msr SSBS, xzr
cpu_reset_func_end neoverse_hermes
cpu_reset_func_end neoverse_n3
/* ----------------------------------------------------
* HW will do the cache maintenance while powering down
* ----------------------------------------------------
*/
func neoverse_hermes_core_pwr_dwn
func neoverse_n3_core_pwr_dwn
/* ---------------------------------------------------
* Enable CPU power down bit in power control register
* ---------------------------------------------------
*/
sysreg_bit_set NEOVERSE_HERMES_CPUPWRCTLR_EL1, NEOVERSE_HERMES_CPUPWRCTLR_EL1_CORE_PWRDN_BIT
sysreg_bit_set NEOVERSE_N3_CPUPWRCTLR_EL1, NEOVERSE_N3_CPUPWRCTLR_EL1_CORE_PWRDN_BIT
isb
ret
endfunc neoverse_hermes_core_pwr_dwn
endfunc neoverse_n3_core_pwr_dwn
errata_report_shim neoverse_hermes
errata_report_shim neoverse_n3
/* ---------------------------------------------
* This function provides Neoverse Hermes specific
* This function provides Neoverse-N3 specific
* register information for crash reporting.
* It needs to return with x6 pointing to
* a list of register names in ascii and
@ -51,16 +51,16 @@ errata_report_shim neoverse_hermes
* reported.
* ---------------------------------------------
*/
.section .rodata.neoverse_hermes_regs, "aS"
neoverse_hermes_regs: /* The ascii list of register names to be reported */
.section .rodata.neoverse_n3_regs, "aS"
neoverse_n3_regs: /* The ascii list of register names to be reported */
.asciz "cpuectlr_el1", ""
func neoverse_hermes_cpu_reg_dump
adr x6, neoverse_hermes_regs
mrs x8, NEOVERSE_HERMES_CPUECTLR_EL1
func neoverse_n3_cpu_reg_dump
adr x6, neoverse_n3_regs
mrs x8, NEOVERSE_N3_CPUECTLR_EL1
ret
endfunc neoverse_hermes_cpu_reg_dump
endfunc neoverse_n3_cpu_reg_dump
declare_cpu_ops neoverse_hermes, NEOVERSE_HERMES_MIDR, \
neoverse_hermes_reset_func, \
neoverse_hermes_core_pwr_dwn
declare_cpu_ops neoverse_n3, NEOVERSE_N3_MIDR, \
neoverse_n3_reset_func, \
neoverse_n3_core_pwr_dwn

2
plat/arm/board/fvp/platform.mk
View file

@ -202,7 +202,7 @@ endif
#Build AArch64-only CPUs with no FVP model yet.
ifeq (${BUILD_CPUS_WITH_NO_FVP_MODEL},1)
FVP_CPU_LIBS += lib/cpus/aarch64/neoverse_hermes.S \
FVP_CPU_LIBS += lib/cpus/aarch64/neoverse_n3.S \
lib/cpus/aarch64/cortex_gelas.S \
lib/cpus/aarch64/nevis.S \
lib/cpus/aarch64/travis.S