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Merge changes from topic "sm/feat_detect" into integration

Browse source 
* changes:
  refactor(cpufeat): restore functions in detect_arch_features
  refactor(cpufeat): add macro to simplify is_feat_xx_present
  chore: simplify the macro names in ENABLE_FEAT mechanism
This commit is contained in:
Manish Pandey 2024-05-07 11:17:02 +02:00 • committed by TrustedFirmware Code Review
commit 2a0ca84f47
23 changed files with 610 additions and 473 deletions
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4
bl31/bl31_traps.c
View file

@ -36,7 +36,7 @@ static bool is_tge_enabled(void)
{
u_register_t hcr_el2 = read_hcr_el2();
return ((read_feat_vhe_id_field() != 0U) && ((hcr_el2 & HCR_TGE_BIT) != 0U));
return ((is_feat_vhe_present()) && ((hcr_el2 & HCR_TGE_BIT) != 0U));
}
/*
@ -116,7 +116,7 @@ u_register_t create_spsr(u_register_t old_spsr, unsigned int target_el)
/* If FEAT_BTI is present, clear BTYPE bits */
new_spsr |= old_spsr & (SPSR_BTYPE_MASK_AARCH64 << SPSR_BTYPE_SHIFT_AARCH64);
if (is_armv8_5_bti_present()) {
if (is_feat_bti_present()) {
new_spsr &= ~(SPSR_BTYPE_MASK_AARCH64 << SPSR_BTYPE_SHIFT_AARCH64);
}

203
common/feat_detect.c
View file

@ -70,35 +70,185 @@ static void read_feat_pauth(void)
#endif
}
/****************************************************
* Feature : FEAT_BTI (Branch Target Identification)
***************************************************/
static void read_feat_bti(void)
static unsigned int read_feat_rng_trap_id_field(void)
{
#if (ENABLE_BTI == FEAT_STATE_ALWAYS)
feat_detect_panic(is_armv8_5_bti_present(), "BTI");
#endif
return ISOLATE_FIELD(read_id_aa64pfr1_el1(), ID_AA64PFR1_EL1_RNDR_TRAP_SHIFT,
ID_AA64PFR1_EL1_RNDR_TRAP_MASK);
}
/**************************************************
* Feature : FEAT_RME (Realm Management Extension)
*************************************************/
static void read_feat_rme(void)
static unsigned int read_feat_bti_id_field(void)
{
#if (ENABLE_RME == FEAT_STATE_ALWAYS)
feat_detect_panic((get_armv9_2_feat_rme_support() !=
ID_AA64PFR0_FEAT_RME_NOT_SUPPORTED), "RME");
#endif
return ISOLATE_FIELD(read_id_aa64pfr1_el1(), ID_AA64PFR1_EL1_BT_SHIFT,
ID_AA64PFR1_EL1_BT_MASK);
}
/******************************************************************
* Feature : FEAT_RNG_TRAP (Trapping support for RNDR/RNDRRS)
*****************************************************************/
static void read_feat_rng_trap(void)
static unsigned int read_feat_sb_id_field(void)
{
#if (ENABLE_FEAT_RNG_TRAP == FEAT_STATE_ALWAYS)
feat_detect_panic(is_feat_rng_trap_present(), "RNG_TRAP");
#endif
return ISOLATE_FIELD(read_id_aa64isar1_el1(), ID_AA64ISAR1_SB_SHIFT,
ID_AA64ISAR1_SB_MASK);
}
static unsigned int read_feat_csv2_id_field(void)
{
return ISOLATE_FIELD(read_id_aa64pfr0_el1(), ID_AA64PFR0_CSV2_SHIFT,
ID_AA64PFR0_CSV2_MASK);
}
static unsigned int read_feat_pmuv3_id_field(void)
{
return ISOLATE_FIELD(read_id_aa64dfr0_el1(), ID_AA64DFR0_PMUVER_SHIFT,
ID_AA64DFR0_PMUVER_MASK);
}
static unsigned int read_feat_vhe_id_field(void)
{
return ISOLATE_FIELD(read_id_aa64mmfr1_el1(), ID_AA64MMFR1_EL1_VHE_SHIFT,
ID_AA64MMFR1_EL1_VHE_MASK);
}
static unsigned int read_feat_sve_id_field(void)
{
return ISOLATE_FIELD(read_id_aa64pfr0_el1(), ID_AA64PFR0_SVE_SHIFT,
ID_AA64PFR0_SVE_MASK);
}
static unsigned int read_feat_ras_id_field(void)
{
return ISOLATE_FIELD(read_id_aa64pfr0_el1(), ID_AA64PFR0_RAS_SHIFT,
ID_AA64PFR0_RAS_MASK);
}
static unsigned int read_feat_dit_id_field(void)
{
return ISOLATE_FIELD(read_id_aa64pfr0_el1(), ID_AA64PFR0_DIT_SHIFT,
ID_AA64PFR0_DIT_MASK);
}
static unsigned int read_feat_amu_id_field(void)
{
return ISOLATE_FIELD(read_id_aa64pfr0_el1(), ID_AA64PFR0_AMU_SHIFT,
ID_AA64PFR0_AMU_MASK);
}
static unsigned int read_feat_mpam_version(void)
{
return (unsigned int)((((read_id_aa64pfr0_el1() >>
ID_AA64PFR0_MPAM_SHIFT) & ID_AA64PFR0_MPAM_MASK) << 4) |
((read_id_aa64pfr1_el1() >>
ID_AA64PFR1_MPAM_FRAC_SHIFT) & ID_AA64PFR1_MPAM_FRAC_MASK));
}
static unsigned int read_feat_nv_id_field(void)
{
return ISOLATE_FIELD(read_id_aa64mmfr2_el1(), ID_AA64MMFR2_EL1_NV_SHIFT,
ID_AA64MMFR2_EL1_NV_MASK);
}
static unsigned int read_feat_sel2_id_field(void)
{
return ISOLATE_FIELD(read_id_aa64pfr0_el1(), ID_AA64PFR0_SEL2_SHIFT,
ID_AA64PFR0_SEL2_MASK);
}
static unsigned int read_feat_trf_id_field(void)
{
return ISOLATE_FIELD(read_id_aa64dfr0_el1(), ID_AA64DFR0_TRACEFILT_SHIFT,
ID_AA64DFR0_TRACEFILT_MASK);
}
static unsigned int get_armv8_5_mte_support(void)
{
return ISOLATE_FIELD(read_id_aa64pfr1_el1(), ID_AA64PFR1_EL1_MTE_SHIFT,
ID_AA64PFR1_EL1_MTE_MASK);
}
static unsigned int read_feat_rng_id_field(void)
{
return ISOLATE_FIELD(read_id_aa64isar0_el1(), ID_AA64ISAR0_RNDR_SHIFT,
ID_AA64ISAR0_RNDR_MASK);
}
static unsigned int read_feat_fgt_id_field(void)
{
return ISOLATE_FIELD(read_id_aa64mmfr0_el1(), ID_AA64MMFR0_EL1_FGT_SHIFT,
ID_AA64MMFR0_EL1_FGT_MASK);
}
static unsigned int read_feat_ecv_id_field(void)
{
return ISOLATE_FIELD(read_id_aa64mmfr0_el1(), ID_AA64MMFR0_EL1_ECV_SHIFT,
ID_AA64MMFR0_EL1_ECV_MASK);
}
static unsigned int read_feat_twed_id_field(void)
{
return ISOLATE_FIELD(read_id_aa64mmfr1_el1(), ID_AA64MMFR1_EL1_TWED_SHIFT,
ID_AA64MMFR1_EL1_TWED_MASK);
}
static unsigned int read_feat_hcx_id_field(void)
{
return ISOLATE_FIELD(read_id_aa64mmfr1_el1(), ID_AA64MMFR1_EL1_HCX_SHIFT,
ID_AA64MMFR1_EL1_HCX_MASK);
}
static unsigned int read_feat_tcr2_id_field(void)
{
return ISOLATE_FIELD(read_id_aa64mmfr3_el1(), ID_AA64MMFR3_EL1_TCRX_SHIFT,
ID_AA64MMFR3_EL1_TCRX_MASK);
}
static unsigned int read_feat_s2pie_id_field(void)
{
return ISOLATE_FIELD(read_id_aa64mmfr3_el1(), ID_AA64MMFR3_EL1_S2PIE_SHIFT,
ID_AA64MMFR3_EL1_S2PIE_MASK);
}
static unsigned int read_feat_s1pie_id_field(void)
{
return ISOLATE_FIELD(read_id_aa64mmfr3_el1(), ID_AA64MMFR3_EL1_S1PIE_SHIFT,
ID_AA64MMFR3_EL1_S1PIE_MASK);
}
static unsigned int read_feat_s2poe_id_field(void)
{
return ISOLATE_FIELD(read_id_aa64mmfr3_el1(), ID_AA64MMFR3_EL1_S2POE_SHIFT,
ID_AA64MMFR3_EL1_S2POE_MASK);
}
static unsigned int read_feat_s1poe_id_field(void)
{
return ISOLATE_FIELD(read_id_aa64mmfr3_el1(), ID_AA64MMFR3_EL1_S1POE_SHIFT,
ID_AA64MMFR3_EL1_S1POE_MASK);
}
static unsigned int read_feat_brbe_id_field(void)
{
return ISOLATE_FIELD(read_id_aa64dfr0_el1(), ID_AA64DFR0_BRBE_SHIFT,
ID_AA64DFR0_BRBE_MASK);
}
static unsigned int read_feat_trbe_id_field(void)
{
return ISOLATE_FIELD(read_id_aa64dfr0_el1(), ID_AA64DFR0_TRACEBUFFER_SHIFT,
ID_AA64DFR0_TRACEBUFFER_MASK);
}
static unsigned int read_feat_sme_id_field(void)
{
return ISOLATE_FIELD(read_id_aa64pfr1_el1(), ID_AA64PFR1_EL1_SME_SHIFT,
ID_AA64PFR1_EL1_SME_MASK);
}
static unsigned int read_feat_gcs_id_field(void)
{
return ISOLATE_FIELD(read_id_aa64pfr1_el1(), ID_AA64PFR1_EL1_GCS_SHIFT,
ID_AA64PFR1_EL1_GCS_MASK);
}
static unsigned int read_feat_rme_id_field(void)
{
return ISOLATE_FIELD(read_id_aa64pfr0_el1(), ID_AA64PFR0_FEAT_RME_SHIFT,
ID_AA64PFR0_FEAT_RME_MASK);
}
static unsigned int read_feat_pan_id_field(void)
{
return ISOLATE_FIELD(read_id_aa64mmfr1_el1(), ID_AA64MMFR1_EL1_PAN_SHIFT,
ID_AA64MMFR1_EL1_PAN_MASK);
}
static unsigned int read_feat_mtpmu_id_field(void)
{
return ISOLATE_FIELD(read_id_aa64dfr0_el1(), ID_AA64DFR0_MTPMU_SHIFT,
ID_AA64DFR0_MTPMU_MASK);
}
/***********************************************************************************
@ -151,6 +301,7 @@ void detect_arch_features(void)
check_feature(ENABLE_FEAT_RAS, read_feat_ras_id_field(), "RAS", 1, 2);
/* v8.3 features */
/* TODO: Pauth yet to convert to tri-state feat detect logic */
read_feat_pauth();
/* v8.4 features */
@ -170,8 +321,9 @@ void detect_arch_features(void)
check_feature(ENABLE_FEAT_MTE2, get_armv8_5_mte_support(), "MTE2",
MTE_IMPLEMENTED_ELX, MTE_IMPLEMENTED_ASY);
check_feature(ENABLE_FEAT_RNG, read_feat_rng_id_field(), "RNG", 1, 1);
read_feat_bti();
read_feat_rng_trap();
check_feature(ENABLE_BTI, read_feat_bti_id_field(), "BTI", 1, 1);
check_feature(ENABLE_FEAT_RNG_TRAP, read_feat_rng_trap_id_field(),
"RNG_TRAP", 1, 1);
/* v8.6 features */
check_feature(ENABLE_FEAT_AMUv1p1, read_feat_amu_id_field(),
@ -219,8 +371,7 @@ void detect_arch_features(void)
/* v9.4 features */
check_feature(ENABLE_FEAT_GCS, read_feat_gcs_id_field(), "GCS", 1, 1);
read_feat_rme();
check_feature(ENABLE_RME, read_feat_rme_id_field(), "RME", 1, 1);
if (tainted) {
panic();

2
drivers/arm/smmu/smmu_v3.c
View file

@ -97,7 +97,7 @@ int __init smmuv3_init(uintptr_t smmu_base)
#if ENABLE_RME
if (get_armv9_2_feat_rme_support() != 0U) {
if (is_feat_rme_present()) {
if ((mmio_read_32(smmu_base + SMMU_ROOT_IDR0) &
SMMU_ROOT_IDR0_ROOT_IMPL) == 0U) {
WARN("Skip SMMU GPC configuration.\n");

15
include/arch/aarch32/arch.h
View file

@ -1,5 +1,5 @@
/*
* Copyright (c) 2016-2023, Arm Limited and Contributors. All rights reserved.
* Copyright (c) 2016-2024, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@ -111,18 +111,18 @@
#define ID_DFR0_PERFMON_PMUV3P5 U(6)
#define ID_DFR0_COPTRC_SHIFT U(12)
#define ID_DFR0_COPTRC_MASK U(0xf)
#define ID_DFR0_COPTRC_SUPPORTED U(1)
#define COPTRC_IMPLEMENTED U(1)
#define ID_DFR0_COPTRC_LENGTH U(4)
#define ID_DFR0_TRACEFILT_SHIFT U(28)
#define ID_DFR0_TRACEFILT_MASK U(0xf)
#define ID_DFR0_TRACEFILT_SUPPORTED U(1)
#define TRACEFILT_IMPLEMENTED U(1)
#define ID_DFR0_TRACEFILT_LENGTH U(4)
/* ID_DFR1_EL1 definitions */
#define ID_DFR1_MTPMU_SHIFT U(0)
#define ID_DFR1_MTPMU_MASK U(0xf)
#define ID_DFR1_MTPMU_SUPPORTED U(1)
#define ID_DFR1_MTPMU_DISABLED U(15)
#define MTPMU_IMPLEMENTED U(1)
#define MTPMU_NOT_IMPLEMENTED U(15)
/* ID_MMFR3 definitions */
#define ID_MMFR3_PAN_SHIFT U(16)
@ -141,14 +141,13 @@
#define ID_PFR0_AMU_SHIFT U(20)
#define ID_PFR0_AMU_LENGTH U(4)
#define ID_PFR0_AMU_MASK U(0xf)
#define ID_PFR0_AMU_NOT_SUPPORTED U(0x0)
#define ID_PFR0_AMU_V1 U(0x1)
#define ID_PFR0_AMU_V1P1 U(0x2)
#define ID_PFR0_DIT_SHIFT U(24)
#define ID_PFR0_DIT_LENGTH U(4)
#define ID_PFR0_DIT_MASK U(0xf)
#define ID_PFR0_DIT_SUPPORTED (U(1) << ID_PFR0_DIT_SHIFT)
#define DIT_IMPLEMENTED (U(1) << ID_PFR0_DIT_SHIFT)
/* ID_PFR1 definitions */
#define ID_PFR1_VIRTEXT_SHIFT U(12)
@ -166,7 +165,7 @@
/* ID_PFR2 definitions */
#define ID_PFR2_SSBS_SHIFT U(4)
#define ID_PFR2_SSBS_MASK U(0xf)
#define SSBS_UNAVAILABLE U(0)
#define SSBS_NOT_IMPLEMENTED U(0)
/* SCTLR definitions */
#define SCTLR_RES1_DEF ((U(1) << 23) | (U(1) << 22) | (U(1) << 4) | \

243
include/arch/aarch32/arch_features.h
View file

@ -12,132 +12,112 @@
#include <arch_helpers.h>
#include <common/feat_detect.h>
#define ISOLATE_FIELD(reg, feat) \
((unsigned int)(((reg) >> (feat ## _SHIFT)) & (feat ## _MASK)))
#define ISOLATE_FIELD(reg, feat, mask) \
((unsigned int)(((reg) >> (feat)) & mask))
#define CREATE_FEATURE_SUPPORTED(name, read_func, guard) \
static inline bool is_ ## name ## _supported(void) \
{ \
if ((guard) == FEAT_STATE_DISABLED) { \
return false; \
} \
if ((guard) == FEAT_STATE_ALWAYS) { \
return true; \
} \
return read_func(); \
}
#define CREATE_FEATURE_PRESENT(name, idreg, idfield, mask, idval) \
static inline bool is_ ## name ## _present(void) \
{ \
return (ISOLATE_FIELD(read_ ## idreg(), idfield, mask) >= idval) \
? true : false; \
}
#define CREATE_FEATURE_FUNCS(name, idreg, idfield, mask, idval, guard) \
CREATE_FEATURE_PRESENT(name, idreg, idfield, mask, idval) \
CREATE_FEATURE_SUPPORTED(name, is_ ## name ## _present, guard)
/*
* +----------------------------+
* | Features supported |
* +----------------------------+
* | GENTIMER |
* +----------------------------+
* | FEAT_TTCNP |
* +----------------------------+
* | FEAT_AMU |
* +----------------------------+
* | FEAT_AMUV1P1 |
* +----------------------------+
* | FEAT_TRF |
* +----------------------------+
* | FEAT_SYS_REG_TRACE |
* +----------------------------+
* | FEAT_DIT |
* +----------------------------+
* | FEAT_PAN |
* +----------------------------+
* | FEAT_SSBS |
* +----------------------------+
* | FEAT_PMUV3 |
* +----------------------------+
* | FEAT_MTPMU |
* +----------------------------+
*/
/* GENTIMER */
static inline bool is_armv7_gentimer_present(void)
{
return ISOLATE_FIELD(read_id_pfr1(), ID_PFR1_GENTIMER) != 0U;
return ISOLATE_FIELD(read_id_pfr1(), ID_PFR1_GENTIMER_SHIFT,
ID_PFR1_GENTIMER_MASK) != 0U;
}
static inline bool is_armv8_2_ttcnp_present(void)
/* FEAT_TTCNP: Translation table common not private */
CREATE_FEATURE_PRESENT(feat_ttcnp, id_mmfr4, ID_MMFR4_CNP_SHIFT,
ID_MMFR4_CNP_MASK, 1U)
/* FEAT_AMU: Activity Monitors Extension */
CREATE_FEATURE_FUNCS(feat_amu, id_pfr0, ID_PFR0_AMU_SHIFT,
ID_PFR0_AMU_MASK, ID_PFR0_AMU_V1, ENABLE_FEAT_AMU)
/* FEAT_AMUV1P1: AMU Extension v1.1 */
CREATE_FEATURE_FUNCS(feat_amuv1p1, id_pfr0, ID_PFR0_AMU_SHIFT,
ID_PFR0_AMU_MASK, ID_PFR0_AMU_V1P1, ENABLE_FEAT_AMUv1p1)
/* FEAT_TRF: Tracefilter */
CREATE_FEATURE_FUNCS(feat_trf, id_dfr0, ID_DFR0_TRACEFILT_SHIFT,
ID_DFR0_TRACEFILT_MASK, 1U, ENABLE_TRF_FOR_NS)
/* FEAT_SYS_REG_TRACE */
CREATE_FEATURE_FUNCS(feat_sys_reg_trace, id_dfr0, ID_DFR0_COPTRC_SHIFT,
ID_DFR0_COPTRC_MASK, 1U, ENABLE_SYS_REG_TRACE_FOR_NS)
/* FEAT_DIT: Data independent timing */
CREATE_FEATURE_FUNCS(feat_dit, id_pfr0, ID_PFR0_DIT_SHIFT,
ID_PFR0_DIT_MASK, 1U, ENABLE_FEAT_DIT)
/* FEAT_PAN: Privileged access never */
CREATE_FEATURE_FUNCS(feat_pan, id_mmfr3, ID_MMFR3_PAN_SHIFT,
ID_MMFR3_PAN_MASK, 1U, ENABLE_FEAT_PAN)
/* FEAT_SSBS: Speculative store bypass safe */
CREATE_FEATURE_PRESENT(feat_ssbs, id_pfr2, ID_PFR2_SSBS_SHIFT,
ID_PFR2_SSBS_MASK, 1U)
/* FEAT_PMUV3 */
CREATE_FEATURE_PRESENT(feat_pmuv3, id_dfr0, ID_DFR0_PERFMON_SHIFT,
ID_DFR0_PERFMON_MASK, 3U)
/* FEAT_MTPMU */
static inline bool is_feat_mtpmu_present(void)
{
return ISOLATE_FIELD(read_id_mmfr4(), ID_MMFR4_CNP) != 0U;
}
static unsigned int read_feat_amu_id_field(void)
{
return ISOLATE_FIELD(read_id_pfr0(), ID_PFR0_AMU);
}
static inline bool is_feat_amu_supported(void)
{
if (ENABLE_FEAT_AMU == FEAT_STATE_DISABLED) {
return false;
}
if (ENABLE_FEAT_AMU == FEAT_STATE_ALWAYS) {
return true;
}
return read_feat_amu_id_field() >= ID_PFR0_AMU_V1;
}
static inline bool is_feat_amuv1p1_supported(void)
{
if (ENABLE_FEAT_AMUv1p1 == FEAT_STATE_DISABLED) {
return false;
}
if (ENABLE_FEAT_AMUv1p1 == FEAT_STATE_ALWAYS) {
return true;
}
return read_feat_amu_id_field() >= ID_PFR0_AMU_V1P1;
}
static inline unsigned int read_feat_trf_id_field(void)
{
return ISOLATE_FIELD(read_id_dfr0(), ID_DFR0_TRACEFILT);
}
static inline bool is_feat_trf_supported(void)
{
if (ENABLE_TRF_FOR_NS == FEAT_STATE_DISABLED) {
return false;
}
if (ENABLE_TRF_FOR_NS == FEAT_STATE_ALWAYS) {
return true;
}
return read_feat_trf_id_field() != 0U;
}
static inline unsigned int read_feat_coptrc_id_field(void)
{
return ISOLATE_FIELD(read_id_dfr0(), ID_DFR0_COPTRC);
}
static inline bool is_feat_sys_reg_trace_supported(void)
{
if (ENABLE_SYS_REG_TRACE_FOR_NS == FEAT_STATE_DISABLED) {
return false;
}
if (ENABLE_SYS_REG_TRACE_FOR_NS == FEAT_STATE_ALWAYS) {
return true;
}
return read_feat_coptrc_id_field() != 0U;
}
static inline unsigned int read_feat_dit_id_field(void)
{
return ISOLATE_FIELD(read_id_pfr0(), ID_PFR0_DIT);
}
static inline bool is_feat_dit_supported(void)
{
if (ENABLE_FEAT_DIT == FEAT_STATE_DISABLED) {
return false;
}
if (ENABLE_FEAT_DIT == FEAT_STATE_ALWAYS) {
return true;
}
return read_feat_dit_id_field() != 0U;
}
static inline unsigned int read_feat_pan_id_field(void)
{
return ISOLATE_FIELD(read_id_mmfr3(), ID_MMFR3_PAN);
}
static inline bool is_feat_pan_supported(void)
{
if (ENABLE_FEAT_PAN == FEAT_STATE_DISABLED) {
return false;
}
if (ENABLE_FEAT_PAN == FEAT_STATE_ALWAYS) {
return true;
}
return read_feat_pan_id_field() != 0U;
}
static inline bool is_feat_pan_present(void)
{
return read_feat_pan_id_field() != 0U;
}
static inline unsigned int is_feat_ssbs_present(void)
{
return ((read_id_pfr2() >> ID_PFR2_SSBS_SHIFT) &
ID_PFR2_SSBS_MASK) != SSBS_UNAVAILABLE;
unsigned int mtpmu = ISOLATE_FIELD(read_id_dfr1(), ID_DFR1_MTPMU_SHIFT,
ID_DFR1_MTPMU_MASK);
return (mtpmu != 0U) && (mtpmu != MTPMU_NOT_IMPLEMENTED);
}
CREATE_FEATURE_SUPPORTED(feat_mtpmu, is_feat_mtpmu_present, DISABLE_MTPMU)
/*
* TWED, ECV, CSV2, RAS are only used by the AArch64 EL2 context switch
@ -179,29 +159,4 @@ static inline bool is_feat_nmi_present(void) { return false; }
static inline bool is_feat_ebep_present(void) { return false; }
static inline bool is_feat_sebep_present(void) { return false; }
static inline unsigned int read_feat_pmuv3_id_field(void)
{
return ISOLATE_FIELD(read_id_dfr0(), ID_DFR0_PERFMON);
}
static inline unsigned int read_feat_mtpmu_id_field(void)
{
return ISOLATE_FIELD(read_id_dfr1(), ID_DFR1_MTPMU);
}
static inline bool is_feat_mtpmu_supported(void)
{
if (DISABLE_MTPMU == FEAT_STATE_DISABLED) {
return false;
}
if (DISABLE_MTPMU == FEAT_STATE_ALWAYS) {
return true;
}
unsigned int mtpmu = read_feat_mtpmu_id_field();
return mtpmu != 0U && mtpmu != ID_DFR1_MTPMU_DISABLED;
}
#endif /* ARCH_FEATURES_H */

8
include/arch/aarch32/el3_common_macros.S
View file

@ -1,5 +1,5 @@
/*
* Copyright (c) 2016-2023, ARM Limited and Contributors. All rights reserved.
* Copyright (c) 2016-2024, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@ -76,7 +76,7 @@
orr r0, r0, #(NSACR_RESET_VAL | NSACR_ENABLE_FP_ACCESS)
ldcopr r1, ID_DFR0
ubfx r1, r1, #ID_DFR0_COPTRC_SHIFT, #ID_DFR0_COPTRC_LENGTH
cmp r1, #ID_DFR0_COPTRC_SUPPORTED
cmp r1, #COPTRC_IMPLEMENTED
bne 1f
orr r0, r0, #NSTRCDIS_BIT
1:
@ -143,7 +143,7 @@
SDCR_SCCD_BIT) & ~SDCR_TTRF_BIT)
ldcopr r1, ID_DFR0
ubfx r1, r1, #ID_DFR0_TRACEFILT_SHIFT, #ID_DFR0_TRACEFILT_LENGTH
cmp r1, #ID_DFR0_TRACEFILT_SUPPORTED
cmp r1, #TRACEFILT_IMPLEMENTED
bne 1f
orr r0, r0, #SDCR_TTRF_BIT
1:
@ -182,7 +182,7 @@
*/
ldcopr r0, ID_PFR0
and r0, r0, #(ID_PFR0_DIT_MASK << ID_PFR0_DIT_SHIFT)
cmp r0, #ID_PFR0_DIT_SUPPORTED
cmp r0, #DIT_IMPLEMENTED
bne 1f
mrs r0, cpsr
orr r0, r0, #CPSR_DIT_BIT

88
include/arch/aarch64/arch.h
View file

@ -179,7 +179,6 @@
#define ID_AA64PFR0_AMU_SHIFT U(44)
#define ID_AA64PFR0_AMU_MASK ULL(0xf)
#define ID_AA64PFR0_AMU_NOT_SUPPORTED U(0x0)
#define ID_AA64PFR0_AMU_V1 ULL(0x1)
#define ID_AA64PFR0_AMU_V1P1 U(0x2)
@ -191,8 +190,8 @@
#define ID_AA64PFR0_SVE_SHIFT U(32)
#define ID_AA64PFR0_SVE_MASK ULL(0xf)
#define ID_AA64PFR0_SVE_SUPPORTED ULL(0x1)
#define ID_AA64PFR0_SVE_LENGTH U(4)
#define SVE_IMPLEMENTED ULL(0x1)
#define ID_AA64PFR0_SEL2_SHIFT U(36)
#define ID_AA64PFR0_SEL2_MASK ULL(0xf)
@ -203,23 +202,21 @@
#define ID_AA64PFR0_DIT_SHIFT U(48)
#define ID_AA64PFR0_DIT_MASK ULL(0xf)
#define ID_AA64PFR0_DIT_LENGTH U(4)
#define ID_AA64PFR0_DIT_SUPPORTED U(1)
#define DIT_IMPLEMENTED ULL(1)
#define ID_AA64PFR0_CSV2_SHIFT U(56)
#define ID_AA64PFR0_CSV2_MASK ULL(0xf)
#define ID_AA64PFR0_CSV2_LENGTH U(4)
#define ID_AA64PFR0_CSV2_2_SUPPORTED ULL(0x2)
#define ID_AA64PFR0_CSV2_3_SUPPORTED ULL(0x3)
#define CSV2_2_IMPLEMENTED ULL(0x2)
#define CSV2_3_IMPLEMENTED ULL(0x3)
#define ID_AA64PFR0_FEAT_RME_SHIFT U(52)
#define ID_AA64PFR0_FEAT_RME_MASK ULL(0xf)
#define ID_AA64PFR0_FEAT_RME_LENGTH U(4)
#define ID_AA64PFR0_FEAT_RME_NOT_SUPPORTED U(0)
#define ID_AA64PFR0_FEAT_RME_V1 U(1)
#define RME_NOT_IMPLEMENTED ULL(0)
#define ID_AA64PFR0_RAS_SHIFT U(28)
#define ID_AA64PFR0_RAS_MASK ULL(0xf)
#define ID_AA64PFR0_RAS_NOT_SUPPORTED ULL(0x0)
#define ID_AA64PFR0_RAS_LENGTH U(4)
/* Exception level handling */
@ -230,12 +227,13 @@
/* ID_AA64DFR0_EL1.TraceVer definitions */
#define ID_AA64DFR0_TRACEVER_SHIFT U(4)
#define ID_AA64DFR0_TRACEVER_MASK ULL(0xf)
#define ID_AA64DFR0_TRACEVER_SUPPORTED ULL(1)
#define ID_AA64DFR0_TRACEVER_LENGTH U(4)
#define ID_AA64DFR0_TRACEFILT_SHIFT U(40)
#define ID_AA64DFR0_TRACEFILT_MASK U(0xf)
#define ID_AA64DFR0_TRACEFILT_SUPPORTED U(1)
#define ID_AA64DFR0_TRACEFILT_LENGTH U(4)
#define TRACEFILT_IMPLEMENTED ULL(1)
#define ID_AA64DFR0_PMUVER_LENGTH U(4)
#define ID_AA64DFR0_PMUVER_SHIFT U(8)
#define ID_AA64DFR0_PMUVER_MASK U(0xf)
@ -251,24 +249,24 @@
/* ID_AA64DFR0_EL1.PMS definitions (for ARMv8.2+) */
#define ID_AA64DFR0_PMS_SHIFT U(32)
#define ID_AA64DFR0_PMS_MASK ULL(0xf)
#define ID_AA64DFR0_SPE_SUPPORTED ULL(0x1)
#define ID_AA64DFR0_SPE_NOT_SUPPORTED ULL(0x0)
#define SPE_IMPLEMENTED ULL(0x1)
#define SPE_NOT_IMPLEMENTED ULL(0x0)
/* ID_AA64DFR0_EL1.TraceBuffer definitions */
#define ID_AA64DFR0_TRACEBUFFER_SHIFT U(44)
#define ID_AA64DFR0_TRACEBUFFER_MASK ULL(0xf)
#define ID_AA64DFR0_TRACEBUFFER_SUPPORTED ULL(1)
#define TRACEBUFFER_IMPLEMENTED ULL(1)
/* ID_AA64DFR0_EL1.MTPMU definitions (for ARMv8.6+) */
#define ID_AA64DFR0_MTPMU_SHIFT U(48)
#define ID_AA64DFR0_MTPMU_MASK ULL(0xf)
#define ID_AA64DFR0_MTPMU_SUPPORTED ULL(1)
#define ID_AA64DFR0_MTPMU_DISABLED ULL(15)
#define MTPMU_IMPLEMENTED ULL(1)
#define MTPMU_NOT_IMPLEMENTED ULL(15)
/* ID_AA64DFR0_EL1.BRBE definitions */
#define ID_AA64DFR0_BRBE_SHIFT U(52)
#define ID_AA64DFR0_BRBE_MASK ULL(0xf)
#define ID_AA64DFR0_BRBE_SUPPORTED ULL(1)
#define BRBE_IMPLEMENTED ULL(1)
/* ID_AA64DFR1_EL1 definitions */
#define ID_AA64DFR1_EBEP_SHIFT U(48)
@ -294,8 +292,8 @@
#define ID_AA64ISAR1_SB_SHIFT U(36)
#define ID_AA64ISAR1_SB_MASK ULL(0xf)
#define ID_AA64ISAR1_SB_SUPPORTED ULL(0x1)
#define ID_AA64ISAR1_SB_NOT_SUPPORTED ULL(0x0)
#define SB_IMPLEMENTED ULL(0x1)
#define SB_NOT_IMPLEMENTED ULL(0x0)
/* ID_AA64ISAR2_EL1 definitions */
#define ID_AA64ISAR2_EL1 S3_0_C0_C6_2
@ -323,52 +321,41 @@
#define ID_AA64MMFR0_EL1_ECV_SHIFT U(60)
#define ID_AA64MMFR0_EL1_ECV_MASK ULL(0xf)
#define ID_AA64MMFR0_EL1_ECV_NOT_SUPPORTED ULL(0x0)
#define ID_AA64MMFR0_EL1_ECV_SUPPORTED ULL(0x1)
#define ID_AA64MMFR0_EL1_ECV_SELF_SYNCH ULL(0x2)
#define ID_AA64MMFR0_EL1_ECV_SELF_SYNCH ULL(0x2)
#define ECV_IMPLEMENTED ULL(0x1)
#define ID_AA64MMFR0_EL1_FGT_SHIFT U(56)
#define ID_AA64MMFR0_EL1_FGT_MASK ULL(0xf)
#define ID_AA64MMFR0_EL1_FGT_SUPPORTED ULL(0x1)
#define ID_AA64MMFR0_EL1_FGT_NOT_SUPPORTED ULL(0x0)
#define FGT_IMPLEMENTED ULL(0x1)
#define FGT_NOT_IMPLEMENTED ULL(0x0)
#define ID_AA64MMFR0_EL1_TGRAN4_SHIFT U(28)
#define ID_AA64MMFR0_EL1_TGRAN4_MASK ULL(0xf)
#define ID_AA64MMFR0_EL1_TGRAN4_SUPPORTED ULL(0x0)
#define ID_AA64MMFR0_EL1_TGRAN4_52B_SUPPORTED ULL(0x1)
#define ID_AA64MMFR0_EL1_TGRAN4_NOT_SUPPORTED ULL(0xf)
#define ID_AA64MMFR0_EL1_TGRAN64_SHIFT U(24)
#define ID_AA64MMFR0_EL1_TGRAN64_MASK ULL(0xf)
#define ID_AA64MMFR0_EL1_TGRAN64_SUPPORTED ULL(0x0)
#define ID_AA64MMFR0_EL1_TGRAN64_NOT_SUPPORTED ULL(0xf)
#define ID_AA64MMFR0_EL1_TGRAN16_SHIFT U(20)
#define ID_AA64MMFR0_EL1_TGRAN16_MASK ULL(0xf)
#define ID_AA64MMFR0_EL1_TGRAN16_SUPPORTED ULL(0x1)
#define ID_AA64MMFR0_EL1_TGRAN16_NOT_SUPPORTED ULL(0x0)
#define ID_AA64MMFR0_EL1_TGRAN16_52B_SUPPORTED ULL(0x2)
#define TGRAN16_IMPLEMENTED ULL(0x1)
/* ID_AA64MMFR1_EL1 definitions */
#define ID_AA64MMFR1_EL1_TWED_SHIFT U(32)
#define ID_AA64MMFR1_EL1_TWED_MASK ULL(0xf)
#define ID_AA64MMFR1_EL1_TWED_SUPPORTED ULL(0x1)
#define ID_AA64MMFR1_EL1_TWED_NOT_SUPPORTED ULL(0x0)
#define TWED_IMPLEMENTED ULL(0x1)
#define ID_AA64MMFR1_EL1_PAN_SHIFT U(20)
#define ID_AA64MMFR1_EL1_PAN_MASK ULL(0xf)
#define ID_AA64MMFR1_EL1_PAN_NOT_SUPPORTED ULL(0x0)
#define ID_AA64MMFR1_EL1_PAN_SUPPORTED ULL(0x1)
#define ID_AA64MMFR1_EL1_PAN2_SUPPORTED ULL(0x2)
#define ID_AA64MMFR1_EL1_PAN3_SUPPORTED ULL(0x3)
#define PAN_IMPLEMENTED ULL(0x1)
#define PAN2_IMPLEMENTED ULL(0x2)
#define PAN3_IMPLEMENTED ULL(0x3)
#define ID_AA64MMFR1_EL1_VHE_SHIFT U(8)
#define ID_AA64MMFR1_EL1_VHE_MASK ULL(0xf)
#define ID_AA64MMFR1_EL1_HCX_SHIFT U(40)
#define ID_AA64MMFR1_EL1_HCX_MASK ULL(0xf)
#define ID_AA64MMFR1_EL1_HCX_SUPPORTED ULL(0x1)
#define ID_AA64MMFR1_EL1_HCX_NOT_SUPPORTED ULL(0x0)
#define HCX_IMPLEMENTED ULL(0x1)
/* ID_AA64MMFR2_EL1 definitions */
#define ID_AA64MMFR2_EL1 S3_0_C0_C7_2
@ -388,9 +375,7 @@
#define ID_AA64MMFR2_EL1_NV_SHIFT U(24)
#define ID_AA64MMFR2_EL1_NV_MASK ULL(0xf)
#define ID_AA64MMFR2_EL1_NV_NOT_SUPPORTED ULL(0x0)
#define ID_AA64MMFR2_EL1_NV_SUPPORTED ULL(0x1)
#define ID_AA64MMFR2_EL1_NV2_SUPPORTED ULL(0x2)
#define NV2_IMPLEMENTED ULL(0x2)
/* ID_AA64MMFR3_EL1 definitions */
#define ID_AA64MMFR3_EL1 S3_0_C0_C7_3
@ -414,11 +399,11 @@
#define ID_AA64PFR1_EL1_BT_SHIFT U(0)
#define ID_AA64PFR1_EL1_BT_MASK ULL(0xf)
#define BTI_IMPLEMENTED ULL(1) /* The BTI mechanism is implemented */
#define BTI_IMPLEMENTED ULL(1) /* The BTI mechanism is implemented */
#define ID_AA64PFR1_EL1_SSBS_SHIFT U(4)
#define ID_AA64PFR1_EL1_SSBS_MASK ULL(0xf)
#define SSBS_UNAVAILABLE ULL(0) /* No architectural SSBS support */
#define SSBS_NOT_IMPLEMENTED ULL(0) /* No architectural SSBS support */
#define ID_AA64PFR1_EL1_MTE_SHIFT U(8)
#define ID_AA64PFR1_EL1_MTE_MASK ULL(0xf)
@ -434,8 +419,7 @@
#define ID_AA64PFR1_EL1_GCS_MASK ULL(0xf)
#define GCS_IMPLEMENTED ULL(1)
#define ID_AA64PFR1_EL1_RNG_TRAP_SUPPORTED ULL(0x1)
#define ID_AA64PFR1_EL1_RNG_TRAP_NOT_SUPPORTED ULL(0x0)
#define RNG_TRAP_IMPLEMENTED ULL(0x1)
/* ID_AA64PFR2_EL1 definitions */
#define ID_AA64PFR2_EL1_MTEPERM_SHIFT U(0)
@ -468,9 +452,9 @@
#define ID_AA64PFR1_EL1_SME_SHIFT U(24)
#define ID_AA64PFR1_EL1_SME_MASK ULL(0xf)
#define ID_AA64PFR1_EL1_SME_WIDTH U(4)
#define ID_AA64PFR1_EL1_SME_NOT_SUPPORTED ULL(0x0)
#define ID_AA64PFR1_EL1_SME_SUPPORTED ULL(0x1)
#define ID_AA64PFR1_EL1_SME2_SUPPORTED ULL(0x2)
#define SME_IMPLEMENTED ULL(0x1)
#define SME2_IMPLEMENTED ULL(0x2)
#define SME_NOT_IMPLEMENTED ULL(0x0)
/* ID_PFR1_EL1 definitions */
#define ID_PFR1_VIRTEXT_SHIFT U(12)
@ -1102,11 +1086,11 @@
/* ID_AA64SMFR0_EL1 definitions */
#define ID_AA64SMFR0_EL1_SME_FA64_SHIFT U(63)
#define ID_AA64SMFR0_EL1_SME_FA64_MASK U(0x1)
#define ID_AA64SMFR0_EL1_SME_FA64_SUPPORTED U(0x1)
#define SME_FA64_IMPLEMENTED U(0x1)
#define ID_AA64SMFR0_EL1_SME_VER_SHIFT U(55)
#define ID_AA64SMFR0_EL1_SME_VER_MASK ULL(0xf)
#define ID_AA64SMFR0_EL1_SME_INST_SUPPORTED ULL(0x0)
#define ID_AA64SMFR0_EL1_SME2_INST_SUPPORTED ULL(0x1)
#define SME_INST_IMPLEMENTED ULL(0x0)
#define SME2_INST_IMPLEMENTED ULL(0x1)
/* SMCR_ELx definitions */
#define SMCR_ELX_LEN_SHIFT U(0)

455
include/arch/aarch64/arch_features.h
View file

@ -12,27 +12,125 @@
#include <arch_helpers.h>
#include <common/feat_detect.h>
#define ISOLATE_FIELD(reg, feat) \
((unsigned int)(((reg) >> (feat)) & ID_REG_FIELD_MASK))
#define ISOLATE_FIELD(reg, feat, mask) \
((unsigned int)(((reg) >> (feat)) & mask))
#define CREATE_FEATURE_FUNCS_VER(name, read_func, idvalue, guard) \
static inline bool is_ ## name ## _supported(void) \
{ \
if ((guard) == FEAT_STATE_DISABLED) { \
return false; \
} \
if ((guard) == FEAT_STATE_ALWAYS) { \
return true; \
} \
return read_func() >= (idvalue); \
#define CREATE_FEATURE_SUPPORTED(name, read_func, guard) \
static inline bool is_ ## name ## _supported(void) \
{ \
if ((guard) == FEAT_STATE_DISABLED) { \
return false; \
} \
if ((guard) == FEAT_STATE_ALWAYS) { \
return true; \
} \
return read_func(); \
}
#define CREATE_FEATURE_FUNCS(name, idreg, idfield, guard) \
static unsigned int read_ ## name ## _id_field(void) \
{ \
return ISOLATE_FIELD(read_ ## idreg(), idfield); \
} \
CREATE_FEATURE_FUNCS_VER(name, read_ ## name ## _id_field, 1U, guard)
#define CREATE_FEATURE_PRESENT(name, idreg, idfield, mask, idval) \
static inline bool is_ ## name ## _present(void) \
{ \
return (ISOLATE_FIELD(read_ ## idreg(), idfield, mask) >= idval) \
? true : false; \
}
#define CREATE_FEATURE_FUNCS(name, idreg, idfield, mask, idval, guard) \
CREATE_FEATURE_PRESENT(name, idreg, idfield, mask, idval) \
CREATE_FEATURE_SUPPORTED(name, is_ ## name ## _present, guard)
/* +----------------------------+
* | Features supported |
* +----------------------------+
* | GENTIMER |
* +----------------------------+
* | FEAT_PAN |
* +----------------------------+
* | FEAT_VHE |
* +----------------------------+
* | FEAT_TTCNP |
* +----------------------------+
* | FEAT_UAO |
* +----------------------------+
* | FEAT_PACQARMA3 |
* +----------------------------+
* | FEAT_PAUTH |
* +----------------------------+
* | FEAT_TTST |
* +----------------------------+
* | FEAT_BTI |
* +----------------------------+
* | FEAT_MTE2 |
* +----------------------------+
* | FEAT_SSBS |
* +----------------------------+
* | FEAT_NMI |
* +----------------------------+
* | FEAT_GCS |
* +----------------------------+
* | FEAT_EBEP |
* +----------------------------+
* | FEAT_SEBEP |
* +----------------------------+
* | FEAT_SEL2 |
* +----------------------------+
* | FEAT_TWED |
* +----------------------------+
* | FEAT_FGT |
* +----------------------------+
* | FEAT_EC/ECV2 |
* +----------------------------+
* | FEAT_RNG |
* +----------------------------+
* | FEAT_TCR2 |
* +----------------------------+
* | FEAT_S2POE |
* +----------------------------+
* | FEAT_S1POE |
* +----------------------------+
* | FEAT_S2PIE |
* +----------------------------+
* | FEAT_S1PIE |
* +----------------------------+
* | FEAT_AMU/AMUV1P1 |
* +----------------------------+
* | FEAT_MPAM |
* +----------------------------+
* | FEAT_HCX |
* +----------------------------+
* | FEAT_RNG_TRAP |
* +----------------------------+
* | FEAT_RME |
* +----------------------------+
* | FEAT_SB |
* +----------------------------+
* | FEAT_CSV2/CSV3 |
* +----------------------------+
* | FEAT_SPE |
* +----------------------------+
* | FEAT_SVE |
* +----------------------------+
* | FEAT_RAS |
* +----------------------------+
* | FEAT_DIT |
* +----------------------------+
* | FEAT_SYS_REG_TRACE |
* +----------------------------+
* | FEAT_TRF |
* +----------------------------+
* | FEAT_NV/NV2 |
* +----------------------------+
* | FEAT_BRBE |
* +----------------------------+
* | FEAT_TRBE |
* +----------------------------+
* | FEAT_SME/SME2 |
* +----------------------------+
* | FEAT_PMUV3 |
* +----------------------------+
* | FEAT_MTPMU |
* +----------------------------+
*/
static inline bool is_armv7_gentimer_present(void)
{
@ -40,38 +138,28 @@ static inline bool is_armv7_gentimer_present(void)
return true;
}
/* FEAT_PAN: Privileged access never */
CREATE_FEATURE_FUNCS(feat_pan, id_aa64mmfr1_el1, ID_AA64MMFR1_EL1_PAN_SHIFT,
ENABLE_FEAT_PAN)
static inline bool is_feat_pan_present(void)
{
return read_feat_pan_id_field() != 0U;
}
ID_AA64MMFR1_EL1_PAN_MASK, 1U, ENABLE_FEAT_PAN)
/* FEAT_VHE: Virtualization Host Extensions */
CREATE_FEATURE_FUNCS(feat_vhe, id_aa64mmfr1_el1, ID_AA64MMFR1_EL1_VHE_SHIFT,
ENABLE_FEAT_VHE)
ID_AA64MMFR1_EL1_VHE_MASK, 1U, ENABLE_FEAT_VHE)
static inline bool is_armv8_2_ttcnp_present(void)
{
return ((read_id_aa64mmfr2_el1() >> ID_AA64MMFR2_EL1_CNP_SHIFT) &
ID_AA64MMFR2_EL1_CNP_MASK) != 0U;
}
/* FEAT_TTCNP: Translation table common not private */
CREATE_FEATURE_PRESENT(feat_ttcnp, id_aa64mmfr2_el1, ID_AA64MMFR2_EL1_CNP_SHIFT,
ID_AA64MMFR2_EL1_CNP_MASK, 1U)
static inline bool is_feat_uao_present(void)
{
return ((read_id_aa64mmfr2_el1() >> ID_AA64MMFR2_EL1_UAO_SHIFT) &
ID_AA64MMFR2_EL1_UAO_MASK) != 0U;
}
/* FEAT_UAO: User access override */
CREATE_FEATURE_PRESENT(feat_uao, id_aa64mmfr2_el1, ID_AA64MMFR2_EL1_UAO_SHIFT,
ID_AA64MMFR2_EL1_UAO_MASK, 1U)
static inline bool is_feat_pacqarma3_present(void)
{
uint64_t mask_id_aa64isar2 =
(ID_AA64ISAR2_GPA3_MASK << ID_AA64ISAR2_GPA3_SHIFT) |
(ID_AA64ISAR2_APA3_MASK << ID_AA64ISAR2_APA3_SHIFT);
/* If any of the fields is not zero, QARMA3 algorithm is present */
return (read_id_aa64isar2_el1() & mask_id_aa64isar2) != 0U;
}
/* If any of the fields is not zero, QARMA3 algorithm is present */
CREATE_FEATURE_PRESENT(feat_pacqarma3, id_aa64isar2_el1, 0,
((ID_AA64ISAR2_GPA3_MASK << ID_AA64ISAR2_GPA3_SHIFT) |
(ID_AA64ISAR2_APA3_MASK << ID_AA64ISAR2_APA3_SHIFT)), 1U)
/* PAUTH */
static inline bool is_armv8_3_pauth_present(void)
{
uint64_t mask_id_aa64isar1 =
@ -88,89 +176,81 @@ static inline bool is_armv8_3_pauth_present(void)
is_feat_pacqarma3_present());
}
static inline bool is_armv8_4_ttst_present(void)
{
return ((read_id_aa64mmfr2_el1() >> ID_AA64MMFR2_EL1_ST_SHIFT) &
ID_AA64MMFR2_EL1_ST_MASK) == 1U;
}
/* FEAT_TTST: Small translation tables */
CREATE_FEATURE_PRESENT(feat_ttst, id_aa64mmfr2_el1, ID_AA64MMFR2_EL1_ST_SHIFT,
ID_AA64MMFR2_EL1_ST_MASK, 1U)
static inline bool is_armv8_5_bti_present(void)
{
return ((read_id_aa64pfr1_el1() >> ID_AA64PFR1_EL1_BT_SHIFT) &
ID_AA64PFR1_EL1_BT_MASK) == BTI_IMPLEMENTED;
}
/* FEAT_BTI: Branch target identification */
CREATE_FEATURE_PRESENT(feat_bti, id_aa64pfr1_el1, ID_AA64PFR1_EL1_BT_SHIFT,
ID_AA64PFR1_EL1_BT_MASK, BTI_IMPLEMENTED)
static inline unsigned int get_armv8_5_mte_support(void)
{
return ((read_id_aa64pfr1_el1() >> ID_AA64PFR1_EL1_MTE_SHIFT) &
ID_AA64PFR1_EL1_MTE_MASK);
}
static inline unsigned int is_feat_mte2_present(void)
{
return get_armv8_5_mte_support() >= MTE_IMPLEMENTED_ELX;
}
/* FEAT_MTE2: Memory tagging extension */
CREATE_FEATURE_FUNCS(feat_mte2, id_aa64pfr1_el1, ID_AA64PFR1_EL1_MTE_SHIFT,
ID_AA64PFR1_EL1_MTE_MASK, MTE_IMPLEMENTED_ELX, ENABLE_FEAT_MTE2)
static inline bool is_feat_ssbs_present(void)
{
return ((read_id_aa64pfr1_el1() >> ID_AA64PFR1_EL1_SSBS_SHIFT) &
ID_AA64PFR1_EL1_SSBS_MASK) != SSBS_UNAVAILABLE;
}
/* FEAT_SSBS: Speculative store bypass safe */
CREATE_FEATURE_PRESENT(feat_ssbs, id_aa64pfr1_el1, ID_AA64PFR1_EL1_SSBS_SHIFT,
ID_AA64PFR1_EL1_SSBS_MASK, 1U)
static inline bool is_feat_nmi_present(void)
{
return ((read_id_aa64pfr1_el1() >> ID_AA64PFR1_EL1_NMI_SHIFT) &
ID_AA64PFR1_EL1_NMI_MASK) == NMI_IMPLEMENTED;
}
/* FEAT_NMI: Non-maskable interrupts */
CREATE_FEATURE_PRESENT(feat_nmi, id_aa64pfr1_el1, ID_AA64PFR1_EL1_NMI_SHIFT,
ID_AA64PFR1_EL1_NMI_MASK, NMI_IMPLEMENTED)
static inline bool is_feat_gcs_present(void)
{
return ((read_id_aa64pfr1_el1() >> ID_AA64PFR1_EL1_GCS_SHIFT) &
ID_AA64PFR1_EL1_GCS_MASK) == GCS_IMPLEMENTED;
}
/* FEAT_EBEP */
CREATE_FEATURE_PRESENT(feat_ebep, id_aa64dfr1_el1, ID_AA64DFR1_EBEP_SHIFT,
ID_AA64DFR1_EBEP_MASK, EBEP_IMPLEMENTED)
static inline bool is_feat_ebep_present(void)
{
return ((read_id_aa64dfr1_el1() >> ID_AA64DFR1_EBEP_SHIFT) &
ID_AA64DFR1_EBEP_MASK) == EBEP_IMPLEMENTED;
}
/* FEAT_SEBEP */
CREATE_FEATURE_PRESENT(feat_sebep, id_aa64dfr0_el1, ID_AA64DFR0_SEBEP_SHIFT,
ID_AA64DFR0_SEBEP_MASK, SEBEP_IMPLEMENTED)
static inline bool is_feat_sebep_present(void)
{
return ((read_id_aa64dfr0_el1() >> ID_AA64DFR0_SEBEP_SHIFT) &
ID_AA64DFR0_SEBEP_MASK) == SEBEP_IMPLEMENTED;
}
CREATE_FEATURE_FUNCS_VER(feat_mte2, get_armv8_5_mte_support, MTE_IMPLEMENTED_ELX,
ENABLE_FEAT_MTE2)
/* FEAT_SEL2: Secure EL2 */
CREATE_FEATURE_FUNCS(feat_sel2, id_aa64pfr0_el1, ID_AA64PFR0_SEL2_SHIFT,
ENABLE_FEAT_SEL2)
ID_AA64PFR0_SEL2_MASK, 1U, ENABLE_FEAT_SEL2)
/* FEAT_TWED: Delayed trapping of WFE */
CREATE_FEATURE_FUNCS(feat_twed, id_aa64mmfr1_el1, ID_AA64MMFR1_EL1_TWED_SHIFT,
ENABLE_FEAT_TWED)
ID_AA64MMFR1_EL1_TWED_MASK, 1U, ENABLE_FEAT_TWED)
/* FEAT_FGT: Fine-grained traps */
CREATE_FEATURE_FUNCS(feat_fgt, id_aa64mmfr0_el1, ID_AA64MMFR0_EL1_FGT_SHIFT,
ENABLE_FEAT_FGT)
ID_AA64MMFR0_EL1_FGT_MASK, 1U, ENABLE_FEAT_FGT)
/* FEAT_ECV: Enhanced Counter Virtualization */
CREATE_FEATURE_FUNCS(feat_ecv, id_aa64mmfr0_el1, ID_AA64MMFR0_EL1_ECV_SHIFT,
ENABLE_FEAT_ECV)
CREATE_FEATURE_FUNCS_VER(feat_ecv_v2, read_feat_ecv_id_field,
ID_AA64MMFR0_EL1_ECV_SELF_SYNCH, ENABLE_FEAT_ECV)
ID_AA64MMFR0_EL1_ECV_MASK, 1U, ENABLE_FEAT_ECV)
CREATE_FEATURE_FUNCS(feat_ecv_v2, id_aa64mmfr0_el1, ID_AA64MMFR0_EL1_ECV_SHIFT,
ID_AA64MMFR0_EL1_ECV_MASK, ID_AA64MMFR0_EL1_ECV_SELF_SYNCH, ENABLE_FEAT_ECV)
/* FEAT_RNG: Random number generator */
CREATE_FEATURE_FUNCS(feat_rng, id_aa64isar0_el1, ID_AA64ISAR0_RNDR_SHIFT,
ENABLE_FEAT_RNG)
CREATE_FEATURE_FUNCS(feat_tcr2, id_aa64mmfr3_el1, ID_AA64MMFR3_EL1_TCRX_SHIFT,
ENABLE_FEAT_TCR2)
ID_AA64ISAR0_RNDR_MASK, 1U, ENABLE_FEAT_RNG)
/* FEAT_TCR2: Support TCR2_ELx regs */
CREATE_FEATURE_FUNCS(feat_tcr2, id_aa64mmfr3_el1, ID_AA64MMFR3_EL1_TCRX_SHIFT,
ID_AA64MMFR3_EL1_TCRX_MASK, 1U, ENABLE_FEAT_TCR2)
/* FEAT_S2POE */
CREATE_FEATURE_FUNCS(feat_s2poe, id_aa64mmfr3_el1, ID_AA64MMFR3_EL1_S2POE_SHIFT,
ENABLE_FEAT_S2POE)
ID_AA64MMFR3_EL1_S2POE_MASK, 1U, ENABLE_FEAT_S2POE)
/* FEAT_S1POE */
CREATE_FEATURE_FUNCS(feat_s1poe, id_aa64mmfr3_el1, ID_AA64MMFR3_EL1_S1POE_SHIFT,
ENABLE_FEAT_S1POE)
ID_AA64MMFR3_EL1_S1POE_MASK, 1U, ENABLE_FEAT_S1POE)
static inline bool is_feat_sxpoe_supported(void)
{
return is_feat_s1poe_supported() || is_feat_s2poe_supported();
}
/* FEAT_S2PIE */
CREATE_FEATURE_FUNCS(feat_s2pie, id_aa64mmfr3_el1, ID_AA64MMFR3_EL1_S2PIE_SHIFT,
ENABLE_FEAT_S2PIE)
ID_AA64MMFR3_EL1_S2PIE_MASK, 1U, ENABLE_FEAT_S2PIE)
/* FEAT_S1PIE */
CREATE_FEATURE_FUNCS(feat_s1pie, id_aa64mmfr3_el1, ID_AA64MMFR3_EL1_S1PIE_SHIFT,
ENABLE_FEAT_S1PIE)
ID_AA64MMFR3_EL1_S1PIE_MASK, 1U, ENABLE_FEAT_S1PIE)
static inline bool is_feat_sxpie_supported(void)
{
return is_feat_s1pie_supported() || is_feat_s2pie_supported();
@ -178,13 +258,15 @@ static inline bool is_feat_sxpie_supported(void)
/* FEAT_GCS: Guarded Control Stack */
CREATE_FEATURE_FUNCS(feat_gcs, id_aa64pfr1_el1, ID_AA64PFR1_EL1_GCS_SHIFT,
ENABLE_FEAT_GCS)
ID_AA64PFR1_EL1_GCS_MASK, 1U, ENABLE_FEAT_GCS)
/* FEAT_AMU: Activity Monitors Extension */
CREATE_FEATURE_FUNCS(feat_amu, id_aa64pfr0_el1, ID_AA64PFR0_AMU_SHIFT,
ENABLE_FEAT_AMU)
CREATE_FEATURE_FUNCS_VER(feat_amuv1p1, read_feat_amu_id_field,
ID_AA64PFR0_AMU_V1P1, ENABLE_FEAT_AMUv1p1)
ID_AA64PFR0_AMU_MASK, 1U, ENABLE_FEAT_AMU)
/* FEAT_AMUV1P1: AMU Extension v1.1 */
CREATE_FEATURE_FUNCS(feat_amuv1p1, id_aa64pfr0_el1, ID_AA64PFR0_AMU_SHIFT,
ID_AA64PFR0_AMU_MASK, ID_AA64PFR0_AMU_V1P1, ENABLE_FEAT_AMUv1p1)
/*
* Return MPAM version:
@ -195,46 +277,32 @@ CREATE_FEATURE_FUNCS_VER(feat_amuv1p1, read_feat_amu_id_field,
* 0x11: v1.1 Armv8.4 or later
*
*/
static inline unsigned int read_feat_mpam_version(void)
static inline bool is_feat_mpam_present(void)
{
return (unsigned int)((((read_id_aa64pfr0_el1() >>
unsigned int ret = (unsigned int)((((read_id_aa64pfr0_el1() >>
ID_AA64PFR0_MPAM_SHIFT) & ID_AA64PFR0_MPAM_MASK) << 4) |
((read_id_aa64pfr1_el1() >>
ID_AA64PFR1_MPAM_FRAC_SHIFT) & ID_AA64PFR1_MPAM_FRAC_MASK));
((read_id_aa64pfr1_el1() >> ID_AA64PFR1_MPAM_FRAC_SHIFT)
& ID_AA64PFR1_MPAM_FRAC_MASK));
return ret;
}
CREATE_FEATURE_FUNCS_VER(feat_mpam, read_feat_mpam_version, 1U,
ENABLE_FEAT_MPAM)
CREATE_FEATURE_SUPPORTED(feat_mpam, is_feat_mpam_present, ENABLE_FEAT_MPAM)
/* FEAT_HCX: Extended Hypervisor Configuration Register */
CREATE_FEATURE_FUNCS(feat_hcx, id_aa64mmfr1_el1, ID_AA64MMFR1_EL1_HCX_SHIFT,
ENABLE_FEAT_HCX)
ID_AA64MMFR1_EL1_HCX_MASK, 1U, ENABLE_FEAT_HCX)
static inline bool is_feat_rng_trap_present(void)
{
return (((read_id_aa64pfr1_el1() >> ID_AA64PFR1_EL1_RNDR_TRAP_SHIFT) &
ID_AA64PFR1_EL1_RNDR_TRAP_MASK)
== ID_AA64PFR1_EL1_RNG_TRAP_SUPPORTED);
}
/* FEAT_RNG_TRAP: Trapping support */
CREATE_FEATURE_PRESENT(feat_rng_trap, id_aa64pfr1_el1, ID_AA64PFR1_EL1_RNDR_TRAP_SHIFT,
ID_AA64PFR1_EL1_RNDR_TRAP_MASK, RNG_TRAP_IMPLEMENTED)
static inline unsigned int get_armv9_2_feat_rme_support(void)
{
/*
* Return the RME version, zero if not supported. This function can be
* used as both an integer value for the RME version or compared to zero
* to detect RME presence.
*/
return (unsigned int)(read_id_aa64pfr0_el1() >>
ID_AA64PFR0_FEAT_RME_SHIFT) & ID_AA64PFR0_FEAT_RME_MASK;
}
/* Return the RME version, zero if not supported. */
CREATE_FEATURE_FUNCS(feat_rme, id_aa64pfr0_el1, ID_AA64PFR0_FEAT_RME_SHIFT,
ID_AA64PFR0_FEAT_RME_MASK, 1U, ENABLE_RME)
/*********************************************************************************
* Function to identify the presence of FEAT_SB (Speculation Barrier Instruction)
********************************************************************************/
static inline unsigned int read_feat_sb_id_field(void)
{
return ISOLATE_FIELD(read_id_aa64isar1_el1(), ID_AA64ISAR1_SB_SHIFT);
}
/* FEAT_SB: Speculation barrier instruction */
CREATE_FEATURE_PRESENT(feat_sb, id_aa64isar1_el1, ID_AA64ISAR1_SB_SHIFT,
ID_AA64ISAR1_SB_MASK, 1U)
/*
* FEAT_CSV2: Cache Speculation Variant 2. This checks bit fields[56-59]
@ -248,109 +316,94 @@ static inline unsigned int read_feat_sb_id_field(void)
* implemented.
* 0b0011 - Feature FEAT_CSV2_3 is implemented.
*/
static inline unsigned int read_feat_csv2_id_field(void)
{
return (unsigned int)(read_id_aa64pfr0_el1() >>
ID_AA64PFR0_CSV2_SHIFT) & ID_AA64PFR0_CSV2_MASK;
}
CREATE_FEATURE_FUNCS_VER(feat_csv2_2, read_feat_csv2_id_field,
ID_AA64PFR0_CSV2_2_SUPPORTED, ENABLE_FEAT_CSV2_2)
CREATE_FEATURE_FUNCS_VER(feat_csv2_3, read_feat_csv2_id_field,
ID_AA64PFR0_CSV2_3_SUPPORTED, ENABLE_FEAT_CSV2_3)
CREATE_FEATURE_FUNCS(feat_csv2_2, id_aa64pfr0_el1, ID_AA64PFR0_CSV2_SHIFT,
ID_AA64PFR0_CSV2_MASK, CSV2_2_IMPLEMENTED, ENABLE_FEAT_CSV2_2)
CREATE_FEATURE_FUNCS(feat_csv2_3, id_aa64pfr0_el1, ID_AA64PFR0_CSV2_SHIFT,
ID_AA64PFR0_CSV2_MASK, CSV2_3_IMPLEMENTED, ENABLE_FEAT_CSV2_3)
/* FEAT_SPE: Statistical Profiling Extension */
CREATE_FEATURE_FUNCS(feat_spe, id_aa64dfr0_el1, ID_AA64DFR0_PMS_SHIFT,
ENABLE_SPE_FOR_NS)
ID_AA64DFR0_PMS_MASK, 1U, ENABLE_SPE_FOR_NS)
/* FEAT_SVE: Scalable Vector Extension */
CREATE_FEATURE_FUNCS(feat_sve, id_aa64pfr0_el1, ID_AA64PFR0_SVE_SHIFT,
ENABLE_SVE_FOR_NS)
ID_AA64PFR0_SVE_MASK, 1U, ENABLE_SVE_FOR_NS)
/* FEAT_RAS: Reliability, Accessibility, Serviceability */
CREATE_FEATURE_FUNCS(feat_ras, id_aa64pfr0_el1,
ID_AA64PFR0_RAS_SHIFT, ENABLE_FEAT_RAS)
CREATE_FEATURE_FUNCS(feat_ras, id_aa64pfr0_el1, ID_AA64PFR0_RAS_SHIFT,
ID_AA64PFR0_RAS_MASK, 1U, ENABLE_FEAT_RAS)
/* FEAT_DIT: Data Independent Timing instructions */
CREATE_FEATURE_FUNCS(feat_dit, id_aa64pfr0_el1,
ID_AA64PFR0_DIT_SHIFT, ENABLE_FEAT_DIT)
CREATE_FEATURE_FUNCS(feat_dit, id_aa64pfr0_el1, ID_AA64PFR0_DIT_SHIFT,
ID_AA64PFR0_DIT_MASK, 1U, ENABLE_FEAT_DIT)
CREATE_FEATURE_FUNCS(feat_sys_reg_trace, id_aa64dfr0_el1,
ID_AA64DFR0_TRACEVER_SHIFT, ENABLE_SYS_REG_TRACE_FOR_NS)
/* FEAT_SYS_REG_TRACE */
CREATE_FEATURE_FUNCS(feat_sys_reg_trace, id_aa64dfr0_el1, ID_AA64DFR0_TRACEVER_SHIFT,
ID_AA64DFR0_TRACEVER_MASK, 1U, ENABLE_SYS_REG_TRACE_FOR_NS)
/* FEAT_TRF: TraceFilter */
CREATE_FEATURE_FUNCS(feat_trf, id_aa64dfr0_el1, ID_AA64DFR0_TRACEFILT_SHIFT,
ENABLE_TRF_FOR_NS)
ID_AA64DFR0_TRACEFILT_MASK, 1U, ENABLE_TRF_FOR_NS)
/* FEAT_NV2: Enhanced Nested Virtualization */
CREATE_FEATURE_FUNCS(feat_nv, id_aa64mmfr2_el1, ID_AA64MMFR2_EL1_NV_SHIFT, 0)
CREATE_FEATURE_FUNCS_VER(feat_nv2, read_feat_nv_id_field,
ID_AA64MMFR2_EL1_NV2_SUPPORTED, CTX_INCLUDE_NEVE_REGS)
CREATE_FEATURE_FUNCS(feat_nv, id_aa64mmfr2_el1, ID_AA64MMFR2_EL1_NV_SHIFT,
ID_AA64MMFR2_EL1_NV_MASK, 1U, 0U)
CREATE_FEATURE_FUNCS(feat_nv2, id_aa64mmfr2_el1, ID_AA64MMFR2_EL1_NV_SHIFT,
ID_AA64MMFR2_EL1_NV_MASK, NV2_IMPLEMENTED, CTX_INCLUDE_NEVE_REGS)
/* FEAT_BRBE: Branch Record Buffer Extension */
CREATE_FEATURE_FUNCS(feat_brbe, id_aa64dfr0_el1, ID_AA64DFR0_BRBE_SHIFT,
ENABLE_BRBE_FOR_NS)
ID_AA64DFR0_BRBE_MASK, 1U, ENABLE_BRBE_FOR_NS)
/* FEAT_TRBE: Trace Buffer Extension */
CREATE_FEATURE_FUNCS(feat_trbe, id_aa64dfr0_el1, ID_AA64DFR0_TRACEBUFFER_SHIFT,
ENABLE_TRBE_FOR_NS)
ID_AA64DFR0_TRACEBUFFER_MASK, 1U, ENABLE_TRBE_FOR_NS)
/* FEAT_SME_FA64: Full A64 Instruction support in streaming SVE mode */
CREATE_FEATURE_PRESENT(feat_sme_fa64, id_aa64smfr0_el1, ID_AA64SMFR0_EL1_SME_FA64_SHIFT,
ID_AA64SMFR0_EL1_SME_FA64_MASK, 1U)
static inline unsigned int read_feat_sme_fa64_id_field(void)
{
return ISOLATE_FIELD(read_id_aa64smfr0_el1(),
ID_AA64SMFR0_EL1_SME_FA64_SHIFT);
}
/* FEAT_SMEx: Scalar Matrix Extension */
CREATE_FEATURE_FUNCS(feat_sme, id_aa64pfr1_el1, ID_AA64PFR1_EL1_SME_SHIFT,
ENABLE_SME_FOR_NS)
CREATE_FEATURE_FUNCS_VER(feat_sme2, read_feat_sme_id_field,
ID_AA64PFR1_EL1_SME2_SUPPORTED, ENABLE_SME2_FOR_NS)
ID_AA64PFR1_EL1_SME_MASK, 1U, ENABLE_SME_FOR_NS)
CREATE_FEATURE_FUNCS(feat_sme2, id_aa64pfr1_el1, ID_AA64PFR1_EL1_SME_SHIFT,
ID_AA64PFR1_EL1_SME_MASK, SME2_IMPLEMENTED, ENABLE_SME2_FOR_NS)
/*******************************************************************************
* Function to get hardware granularity support
******************************************************************************/
static inline unsigned int read_id_aa64mmfr0_el0_tgran4_field(void)
static inline bool is_feat_tgran4K_present(void)
{
return ISOLATE_FIELD(read_id_aa64mmfr0_el1(),
ID_AA64MMFR0_EL1_TGRAN4_SHIFT);
unsigned int tgranx = ISOLATE_FIELD(read_id_aa64mmfr0_el1(),
ID_AA64MMFR0_EL1_TGRAN4_SHIFT, ID_REG_FIELD_MASK);
return (tgranx < 8U);
}
static inline unsigned int read_id_aa64mmfr0_el0_tgran16_field(void)
CREATE_FEATURE_PRESENT(feat_tgran16K, id_aa64mmfr0_el1, ID_AA64MMFR0_EL1_TGRAN16_SHIFT,
ID_AA64MMFR0_EL1_TGRAN16_MASK, TGRAN16_IMPLEMENTED)
static inline bool is_feat_tgran64K_present(void)
{
return ISOLATE_FIELD(read_id_aa64mmfr0_el1(),
ID_AA64MMFR0_EL1_TGRAN16_SHIFT);
unsigned int tgranx = ISOLATE_FIELD(read_id_aa64mmfr0_el1(),
ID_AA64MMFR0_EL1_TGRAN64_SHIFT, ID_REG_FIELD_MASK);
return (tgranx < 8U);
}
static inline unsigned int read_id_aa64mmfr0_el0_tgran64_field(void)
/* FEAT_PMUV3 */
CREATE_FEATURE_PRESENT(feat_pmuv3, id_aa64dfr0_el1, ID_AA64DFR0_PMUVER_SHIFT,
ID_AA64DFR0_PMUVER_MASK, 1U)
/* FEAT_MTPMU */
static inline bool is_feat_mtpmu_present(void)
{
return ISOLATE_FIELD(read_id_aa64mmfr0_el1(),
ID_AA64MMFR0_EL1_TGRAN64_SHIFT);
unsigned int mtpmu = ISOLATE_FIELD(read_id_aa64dfr0_el1(), ID_AA64DFR0_MTPMU_SHIFT,
ID_AA64DFR0_MTPMU_MASK);
return (mtpmu != 0U) && (mtpmu != MTPMU_NOT_IMPLEMENTED);
}
static inline unsigned int read_feat_pmuv3_id_field(void)
{
return ISOLATE_FIELD(read_id_aa64dfr0_el1(), ID_AA64DFR0_PMUVER_SHIFT);
}
static inline unsigned int read_feat_mtpmu_id_field(void)
{
return ISOLATE_FIELD(read_id_aa64dfr0_el1(), ID_AA64DFR0_MTPMU_SHIFT);
}
static inline bool is_feat_mtpmu_supported(void)
{
if (DISABLE_MTPMU == FEAT_STATE_DISABLED) {
return false;
}
if (DISABLE_MTPMU == FEAT_STATE_ALWAYS) {
return true;
}
unsigned int mtpmu = read_feat_mtpmu_id_field();
return (mtpmu != 0U) && (mtpmu != ID_AA64DFR0_MTPMU_DISABLED);
}
CREATE_FEATURE_SUPPORTED(feat_mtpmu, is_feat_mtpmu_present, DISABLE_MTPMU)
#endif /* ARCH_FEATURES_H */

4
include/arch/aarch64/el2_common_macros.S
View file

@ -1,5 +1,5 @@
/*
* Copyright (c) 2021-2023, ARM Limited and Contributors. All rights reserved.
* Copyright (c) 2021-2024, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@ -157,7 +157,7 @@
*/
mrs x0, id_aa64pfr0_el1
ubfx x0, x0, #ID_AA64PFR0_DIT_SHIFT, #ID_AA64PFR0_DIT_LENGTH
cmp x0, #ID_AA64PFR0_DIT_SUPPORTED
cmp x0, #DIT_IMPLEMENTED
bne 1f
mov x0, #DIT_BIT
msr DIT, x0

4
include/arch/aarch64/el3_common_macros.S
View file

@ -1,5 +1,5 @@
/*
* Copyright (c) 2015-2023, Arm Limited and Contributors. All rights reserved.
* Copyright (c) 2015-2024, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@ -133,7 +133,7 @@
#if ENABLE_FEAT_DIT > 1
cbz x0, 1f
#else
cmp x0, #ID_AA64PFR0_DIT_SUPPORTED
cmp x0, #DIT_IMPLEMENTED
ASM_ASSERT(eq)
#endif

4
lib/cpus/aarch64/cortex_gelas.S
View file

@ -1,5 +1,5 @@
/*
* Copyright (c) 2023, Arm Limited. All rights reserved.
* Copyright (c) 2023-2024, Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@ -42,7 +42,7 @@ func cortex_gelas_core_pwr_dwn
mrs x0, ID_AA64PFR1_EL1
ubfx x0, x0, #ID_AA64PFR1_EL1_SME_SHIFT, \
#ID_AA64PFR1_EL1_SME_WIDTH
cmp x0, #ID_AA64PFR1_EL1_SME_NOT_SUPPORTED
cmp x0, #SME_NOT_IMPLEMENTED
b.eq 1f
msr CORTEX_GELAS_SVCRSM, xzr
msr CORTEX_GELAS_SVCRZA, xzr

4
lib/cpus/aarch64/travis.S
View file

@ -1,5 +1,5 @@
/*
* Copyright (c) 2023, Arm Limited. All rights reserved.
* Copyright (c) 2023-2024, Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@ -38,7 +38,7 @@ func travis_core_pwr_dwn
mrs x0, ID_AA64PFR1_EL1
ubfx x0, x0, #ID_AA64PFR1_EL1_SME_SHIFT, \
#ID_AA64PFR1_EL1_SME_WIDTH
cmp x0, #ID_AA64PFR1_EL1_SME_NOT_SUPPORTED
cmp x0, #SME_NOT_IMPLEMENTED
b.eq 1f
msr TRAVIS_SVCRSM, xzr
msr TRAVIS_SVCRZA, xzr

2
lib/el3_runtime/aarch32/context_mgmt.c
View file

@ -149,7 +149,7 @@ static void enable_extensions_nonsecure(bool el2_unused)
trf_init_el3();
}
if (read_feat_pmuv3_id_field() >= 3U) {
if (is_feat_pmuv3_present()) {
pmuv3_init_el3();
}
#endif /* IMAGE_BL32 */

4
lib/extensions/sme/sme.c
View file

@ -1,5 +1,5 @@
/*
* Copyright (c) 2021-2023, Arm Limited and Contributors. All rights reserved.
* Copyright (c) 2021-2024, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@ -53,7 +53,7 @@ void sme_init_el3(void)
* using SMCR_EL2 and SMCR_EL1.
*/
smcr_el3 = SMCR_ELX_LEN_MAX;
if (read_feat_sme_fa64_id_field() != 0U) {
if (is_feat_sme_fa64_present()) {
VERBOSE("[SME] FA64 enabled\n");
smcr_el3 |= SMCR_ELX_FA64_BIT;
}

4
lib/xlat_mpu/aarch64/xlat_mpu_arch.c
View file

@ -1,5 +1,5 @@
/*
* Copyright (c) 2021, Arm Limited and Contributors. All rights reserved.
* Copyright (c) 2021-2024, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@ -27,7 +27,7 @@ uintptr_t xlat_get_min_virt_addr_space_size(void)
{
uintptr_t ret;
if (is_armv8_4_ttst_present()) {
if (is_feat_ttst_present()) {
ret = MIN_VIRT_ADDR_SPACE_SIZE_TTST;
} else {
ret = MIN_VIRT_ADDR_SPACE_SIZE;

4
lib/xlat_tables/aarch64/xlat_tables.c
View file

@ -1,5 +1,5 @@
/*
* Copyright (c) 2014-2021, Arm Limited and Contributors. All rights reserved.
* Copyright (c) 2014-2024, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@ -87,7 +87,7 @@ static uintptr_t xlat_get_min_virt_addr_space_size(void)
{
uintptr_t ret;
if (is_armv8_4_ttst_present())
if (is_feat_ttst_present())
ret = MIN_VIRT_ADDR_SPACE_SIZE_TTST;
else
ret = MIN_VIRT_ADDR_SPACE_SIZE;

4
lib/xlat_tables_v2/aarch32/xlat_tables_arch.c
View file

@ -1,5 +1,5 @@
/*
* Copyright (c) 2017-2021, Arm Limited and Contributors. All rights reserved.
* Copyright (c) 2017-2024, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@ -248,7 +248,7 @@ void setup_mmu_cfg(uint64_t *params, unsigned int flags,
/* Set TTBR0 bits as well */
ttbr0 = (uint64_t)(uintptr_t) base_table;
if (is_armv8_2_ttcnp_present()) {
if (is_feat_ttcnp_present()) {
/* Enable CnP bit so as to share page tables with all PEs. */
ttbr0 |= TTBR_CNP_BIT;
}

17
lib/xlat_tables_v2/aarch64/xlat_tables_arch.c
View file

@ -1,5 +1,5 @@
/*
* Copyright (c) 2017-2023, Arm Limited and Contributors. All rights reserved.
* Copyright (c) 2017-2024, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@ -22,19 +22,14 @@
*/
bool xlat_arch_is_granule_size_supported(size_t size)
{
unsigned int tgranx;
if (size == PAGE_SIZE_4KB) {
tgranx = read_id_aa64mmfr0_el0_tgran4_field();
/* MSB of TGRAN4 field will be '1' for unsupported feature */
return (tgranx < 8U);
return is_feat_tgran4K_present();
} else if (size == PAGE_SIZE_16KB) {
tgranx = read_id_aa64mmfr0_el0_tgran16_field();
return (tgranx >= ID_AA64MMFR0_EL1_TGRAN16_SUPPORTED);
return is_feat_tgran16K_present();
} else if (size == PAGE_SIZE_64KB) {
tgranx = read_id_aa64mmfr0_el0_tgran64_field();
/* MSB of TGRAN64 field will be '1' for unsupported feature */
return (tgranx < 8U);
return is_feat_tgran64K_present();
} else {
return false;
}
@ -135,7 +130,7 @@ uintptr_t xlat_get_min_virt_addr_space_size(void)
{
uintptr_t ret;
if (is_armv8_4_ttst_present())
if (is_feat_ttst_present())
ret = MIN_VIRT_ADDR_SPACE_SIZE_TTST;
else
ret = MIN_VIRT_ADDR_SPACE_SIZE;
@ -312,7 +307,7 @@ void setup_mmu_cfg(uint64_t *params, unsigned int flags,
/* Set TTBR bits as well */
ttbr0 = (uint64_t) base_table;
if (is_armv8_2_ttcnp_present()) {
if (is_feat_ttcnp_present()) {
/* Enable CnP bit so as to share page tables with all PEs. */
ttbr0 |= TTBR_CNP_BIT;
}

4
lib/xlat_tables_v2/xlat_tables_core.c
View file

@ -1,5 +1,5 @@
/*
* Copyright (c) 2017-2021, Arm Limited and Contributors. All rights reserved.
* Copyright (c) 2017-2024, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@ -214,7 +214,7 @@ uint64_t xlat_desc(const xlat_ctx_t *ctx, uint32_t attr,
/* Set GP bit for block and page code entries
* if BTI mechanism is implemented.
*/
if (is_armv8_5_bti_present() &&
if (is_feat_bti_present() &&
((attr & (MT_TYPE_MASK | MT_RW |
MT_EXECUTE_NEVER)) == MT_CODE)) {
desc |= GP;

2
plat/arm/common/arm_bl2_setup.c
View file

@ -217,7 +217,7 @@ void arm_bl2_plat_arch_setup(void)
#ifdef __aarch64__
#if ENABLE_RME
/* BL2 runs in EL3 when RME enabled. */
assert(get_armv9_2_feat_rme_support() != 0U);
assert(is_feat_rme_present());
enable_mmu_el3(0);
/* Initialise and enable granule protection after MMU. */

2
plat/qemu/common/qemu_bl2_setup.c
View file

@ -217,7 +217,7 @@ void bl2_plat_arch_setup(void)
#if ENABLE_RME
/* BL2 runs in EL3 when RME enabled. */
assert(get_armv9_2_feat_rme_support() != 0U);
assert(is_feat_rme_present());
enable_mmu_el3(0);
/* Initialise and enable granule protection after MMU. */

4
services/arm_arch_svc/arm_arch_svc_setup.c
View file

@ -1,5 +1,5 @@
/*
* Copyright (c) 2018-2023, Arm Limited and Contributors. All rights reserved.
* Copyright (c) 2018-2024, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@ -54,7 +54,7 @@ static int32_t smccc_arch_features(u_register_t arg1)
* If architectural SSBS is available on this PE, no firmware
* mitigation via SMCCC_ARCH_WORKAROUND_2 is required.
*/
if (ssbs != SSBS_UNAVAILABLE)
if (ssbs != SSBS_NOT_IMPLEMENTED)
return 1;
/*

2
services/std_svc/rmmd/rmmd_main.c
View file

@ -202,7 +202,7 @@ int rmmd_setup(void)
int rc;
/* Make sure RME is supported. */
assert(get_armv9_2_feat_rme_support() != 0U);
assert(is_feat_rme_present());
rmm_ep_info = bl31_plat_get_next_image_ep_info(REALM);
if (rmm_ep_info == NULL) {