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https://github.com/ARM-software/arm-trusted-firmware.git
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9e51f15ed1
Currently, the macros used to denote feature implementation in hardware follow a random pattern with a few macros having suffix as SUPPORTED and a few using the suffix IMPLEMENTED. This patch aligns the macro names uniformly using the suffix IMPLEMENTED across all the features and removes unused macros pertaining to the Enable feat mechanism. FEAT_SUPPORTED --> FEAT_IMPLEMENTED FEAT_NOT_SUPPORTED --> FEAT_NOT_IMPLEMENTED Change-Id: I61bb7d154b23f677b80756a4b6a81f74b10cd24f Signed-off-by: Sona Mathew <sonarebecca.mathew@arm.com>
71 lines
1.8 KiB
ArmAsm
71 lines
1.8 KiB
ArmAsm
/*
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* Copyright (c) 2023-2024, Arm Limited. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <arch.h>
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#include <asm_macros.S>
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#include <common/bl_common.h>
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#include <travis.h>
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#include <cpu_macros.S>
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#include <plat_macros.S>
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/* Hardware handled coherency */
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#if HW_ASSISTED_COHERENCY == 0
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#error "Travis must be compiled with HW_ASSISTED_COHERENCY enabled"
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#endif
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/* 64-bit only core */
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#if CTX_INCLUDE_AARCH32_REGS == 1
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#error "Travis supports only AArch64. Compile with CTX_INCLUDE_AARCH32_REGS=0"
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#endif
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cpu_reset_func_start travis
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/* ----------------------------------------------------
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* Disable speculative loads
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* ----------------------------------------------------
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*/
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msr SSBS, xzr
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cpu_reset_func_end travis
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func travis_core_pwr_dwn
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#if ENABLE_SME_FOR_NS
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/* ---------------------------------------------------
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* Disable SME if enabled and supported
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* ---------------------------------------------------
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*/
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mrs x0, ID_AA64PFR1_EL1
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ubfx x0, x0, #ID_AA64PFR1_EL1_SME_SHIFT, \
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#ID_AA64PFR1_EL1_SME_WIDTH
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cmp x0, #SME_NOT_IMPLEMENTED
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b.eq 1f
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msr TRAVIS_SVCRSM, xzr
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msr TRAVIS_SVCRZA, xzr
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1:
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#endif
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/* ---------------------------------------------------
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* Enable CPU power down bit in power control register
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* ---------------------------------------------------
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*/
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sysreg_bit_set TRAVIS_IMP_CPUPWRCTLR_EL1, \
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TRAVIS_IMP_CPUPWRCTLR_EL1_CORE_PWRDN_EN_BIT
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isb
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ret
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endfunc travis_core_pwr_dwn
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errata_report_shim travis
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.section .rodata.travis_regs, "aS"
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travis_regs: /* The ASCII list of register names to be reported */
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.asciz "cpuectlr_el1", ""
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func travis_cpu_reg_dump
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adr x6, travis_regs
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mrs x8, TRAVIS_IMP_CPUECTLR_EL1
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ret
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endfunc travis_cpu_reg_dump
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declare_cpu_ops travis, TRAVIS_MIDR, \
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travis_reset_func, \
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travis_core_pwr_dwn
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