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refactor(neoverse-rd): refactor nrd_soc_css_def_v2.h file
Continuing the refactoring of the various definition for platforms based on N2/V2 CPU, refactor the definitions in the nrd_soc_css_def_v2.h file into the following files as appropriate. - nrd_ros_def2.h: includes RoS hardware related definitions - nrd_plat_arm_def2.h: includes platform port related definitions Signed-off-by: Rohit Mathew <rohit.mathew@arm.com> Change-Id: Ib447e67a0a42722735297b27b7f5017bc146156c
This commit is contained in:
Rohit Mathew
parent
d26dae7cb4
commit
13e7d35c6f
6 changed files with 146 additions and 208 deletions
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@ -23,6 +23,9 @@
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#define NRD_DEVICE_BASE UL(0x20000000)
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#define NRD_DEVICE_SIZE UL(0x20000000)
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/* NS RAM Error record */
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#define SOC_NS_RAM_ERR_REC_BASE UL(0x2A4C0000)
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/*Secure Watchdog */
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#define SBSA_SECURE_WDOG_BASE UL(0x2A480000)
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@ -42,6 +42,9 @@
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* RAS config
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******************************************************************************/
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#define NS_RAM_ECC_CE_INT U(87)
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#define NS_RAM_ECC_UE_INT U(88)
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#if (SPM_MM || (SPMC_AT_EL3 && SPMC_AT_EL3_SEL0_SP)) \
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&& ENABLE_FEAT_RAS && FFH_SUPPORT
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/*
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@ -13,7 +13,10 @@
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#ifndef NRD_PLAT_ARM_DEF2_H
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#define NRD_PLAT_ARM_DEF2_H
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#include <nrd_soc_css_def_v2.h>
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#ifndef __ASSEMBLER__
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#include <lib/mmio.h>
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#endif /* __ASSEMBLER__ */
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#include <plat/arm/common/arm_def.h>
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#include <plat/arm/common/arm_spm_def.h>
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#include <plat/arm/css/common/css_def.h>
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@ -221,7 +224,106 @@ ENABLE_FEAT_RAS && FFH_SUPPORT
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* Flash config
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******************************************************************************/
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#define MAX_IO_DEVICES U(3)
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#define MAX_IO_HANDLES U(4)
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#define V2M_SYS_LED U(0x8)
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#define V2M_SYS_LED_SS_SHIFT U(0)
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#define V2M_SYS_LED_EL_SHIFT U(1)
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#define V2M_SYS_LED_EC_SHIFT U(3)
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#define V2M_SYS_LED_SS_MASK U(0x01)
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#define V2M_SYS_LED_EL_MASK U(0x03)
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#define V2M_SYS_LED_EC_MASK U(0x1f)
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#define V2M_SYSREGS_BASE UL(0x0C010000)
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#define V2M_FLASH0_BASE UL(0x08000000)
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#define V2M_FLASH0_SIZE UL(0x04000000)
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#define V2M_FLASH_BLOCK_SIZE UL(0x00040000) /* 256 KB */
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#define PLAT_ARM_FLASH_IMAGE_BASE V2M_FLASH0_BASE
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#define PLAT_ARM_FLASH_IMAGE_MAX_SIZE (V2M_FLASH0_SIZE - V2M_FLASH_BLOCK_SIZE)
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#define PLAT_ARM_MEM_PROT_ADDR (V2M_FLASH0_BASE + \
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V2M_FLASH0_SIZE - V2M_FLASH_BLOCK_SIZE)
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#define PLAT_ARM_NVM_BASE V2M_FLASH0_BASE
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#define PLAT_ARM_NVM_SIZE (V2M_FLASH0_SIZE - V2M_FLASH_BLOCK_SIZE)
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/*******************************************************************************
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* Platform type identification macro
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******************************************************************************/
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/* Platform ID related accessors */
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#define BOARD_CSS_PLAT_ID_REG_ID_MASK U(0x0F)
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#define BOARD_CSS_PLAT_ID_REG_ID_SHIFT U(0x00)
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#define BOARD_CSS_PLAT_ID_REG_VERSION_MASK U(0xF00)
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#define BOARD_CSS_PLAT_ID_REG_VERSION_SHIFT U(0x08)
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#define BOARD_CSS_PLAT_TYPE_RTL U(0x00)
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#define BOARD_CSS_PLAT_TYPE_FPGA U(0x01)
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#define BOARD_CSS_PLAT_TYPE_EMULATOR U(0x02)
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#define BOARD_CSS_PLAT_TYPE_FVP U(0x03)
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#ifndef __ASSEMBLER__
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#define BOARD_CSS_GET_PLAT_TYPE(addr) \
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((mmio_read_32(addr) & BOARD_CSS_PLAT_ID_REG_ID_MASK) \
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>> BOARD_CSS_PLAT_ID_REG_ID_SHIFT)
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#endif /* __ASSEMBLER__ */
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/* Platform ID address */
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#define BOARD_CSS_PLAT_ID_REG_ADDR UL(0x0EFE00E0)
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/*******************************************************************************
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* ROS peripheral config
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******************************************************************************/
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#define SOC_CSS_NIC400_USB_EHCI U(0)
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#define SOC_CSS_NIC400_TLX_MASTER U(1)
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#define SOC_CSS_NIC400_USB_OHCI U(2)
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#define SOC_CSS_NIC400_PL354_SMC U(3)
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#define SOC_CSS_NIC400_APB4_BRIDGE U(4)
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#define SOC_CSS_NIC400_BOOTSEC_BRIDGE U(5)
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#define SOC_CSS_NIC400_BOOTSEC_BRIDGE_UART1 UL(1 << 12)
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#define SOC_CSS_PCIE_CONTROL_BASE UL(0x0ef20000)
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/* SoC NIC-400 Global Programmers View (GPV) */
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#define SOC_CSS_NIC400_BASE UL(0x0ED00000)
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/* Non-volatile counters */
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#define SOC_TRUSTED_NVCTR_BASE UL(0x0EE70000)
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#define TFW_NVCTR_BASE (SOC_TRUSTED_NVCTR_BASE +\
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0x0000)
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#define TFW_NVCTR_SIZE U(4)
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#define NTFW_CTR_BASE (SOC_TRUSTED_NVCTR_BASE +\
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0x0004)
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#define NTFW_CTR_SIZE U(4)
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/* Keys */
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#define SOC_KEYS_BASE UL(0x0EE80000)
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#define TZ_PUB_KEY_HASH_BASE (SOC_KEYS_BASE + 0x0000)
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#define TZ_PUB_KEY_HASH_SIZE U(32)
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#define HU_KEY_BASE (SOC_KEYS_BASE + 0x0020)
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#define HU_KEY_SIZE U(16)
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#define END_KEY_BASE (SOC_KEYS_BASE + 0x0044)
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#define END_KEY_SIZE U(32)
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/*******************************************************************************
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* MMU config
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******************************************************************************/
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#define V2M_MAP_FLASH0_RW \
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MAP_REGION_FLAT( \
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V2M_FLASH0_BASE, \
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V2M_FLASH0_SIZE, \
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MT_DEVICE | MT_RW | MT_SECURE)
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#define V2M_MAP_FLASH0_RO \
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MAP_REGION_FLAT( \
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V2M_FLASH0_BASE, \
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V2M_FLASH0_SIZE, \
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MT_RO_DATA | MT_SECURE)
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#endif /* NRD_PLAT_ARM_DEF2_H */
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@ -26,4 +26,12 @@
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#define SOC_MEMCNTRL_BASE UL(0x10000000)
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#define SOC_MEMCNTRL_SIZE UL(0x10000000)
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/* System peripherals */
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#define SOC_SYSTEM_PERIPH_BASE UL(0x0C000000)
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#define SOC_SYSTEM_PERIPH_SIZE UL(0x02000000)
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/* Platform peripherals */
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#define SOC_PLATFORM_PERIPH_BASE UL(0x0E000000)
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#define SOC_PLATFORM_PERIPH_SIZE UL(0x02000000)
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#endif /* NRD_ROS_DEF2_H */
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@ -17,6 +17,27 @@
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* MMU mapping
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******************************************************************************/
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#define SOC_PLATFORM_PERIPH_MAP_DEVICE \
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MAP_REGION_FLAT( \
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SOC_PLATFORM_PERIPH_BASE, \
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SOC_PLATFORM_PERIPH_SIZE, \
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MT_DEVICE | MT_RW | MT_SECURE)
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#if SPM_MM
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#define SOC_PLATFORM_PERIPH_MAP_DEVICE_USER \
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MAP_REGION_FLAT( \
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SOC_PLATFORM_PERIPH_BASE, \
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SOC_PLATFORM_PERIPH_SIZE, \
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MT_DEVICE | MT_RW | MT_SECURE | MT_USER)
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#endif
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#define SOC_SYSTEM_PERIPH_MAP_DEVICE \
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MAP_REGION_FLAT( \
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SOC_SYSTEM_PERIPH_BASE, \
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SOC_SYSTEM_PERIPH_SIZE, \
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MT_DEVICE | MT_RW | MT_SECURE)
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#define SOC_MEMCNTRL_MAP_DEVICE \
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MAP_REGION_FLAT( \
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SOC_MEMCNTRL_BASE, \
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@ -42,6 +63,14 @@
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CSS_NOR2_FLASH_DEVICE_SIZE, \
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MT_DEVICE | MT_RW | MT_SECURE | MT_USER)
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#define NRD_MAP_FLASH0_RO \
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MAP_REGION_FLAT( \
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V2M_FLASH0_BASE, \
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V2M_FLASH0_SIZE, \
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MT_DEVICE | MT_RO | MT_SECURE)
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/*******************************************************************************
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* TZ config
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******************************************************************************/
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@ -1,207 +0,0 @@
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/*
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* Copyright (c) 2021-2024, Arm Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef NRD_SOC_CSS_DEF_V2_H
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#define NRD_SOC_CSS_DEF_V2_H
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#include <lib/utils_def.h>
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#include <plat/common/common_def.h>
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/*
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* Definitions common to all ARM CSS SoCs
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*/
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/* Following covers ARM CSS SoC Peripherals */
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#define SOC_SYSTEM_PERIPH_BASE UL(0x0C000000)
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#define SOC_SYSTEM_PERIPH_SIZE UL(0x02000000)
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#define SOC_PLATFORM_PERIPH_BASE UL(0x0E000000)
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#define SOC_PLATFORM_PERIPH_SIZE UL(0x02000000)
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#define SOC_CSS_PCIE_CONTROL_BASE UL(0x0ef20000)
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/* Memory controller */
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#define SOC_MEMCNTRL_BASE UL(0x10000000)
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#define SOC_MEMCNTRL_SIZE UL(0x10000000)
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/* SoC NIC-400 Global Programmers View (GPV) */
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#define SOC_CSS_NIC400_BASE UL(0x0ED00000)
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#define SOC_CSS_NIC400_USB_EHCI U(0)
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#define SOC_CSS_NIC400_TLX_MASTER U(1)
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#define SOC_CSS_NIC400_USB_OHCI U(2)
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#define SOC_CSS_NIC400_PL354_SMC U(3)
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/*
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* The apb4_bridge controls access to:
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* - the PCIe configuration registers
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* - the MMU units for USB, HDLCD and DMA
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*/
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#define SOC_CSS_NIC400_APB4_BRIDGE U(4)
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/* Non-volatile counters */
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#define SOC_TRUSTED_NVCTR_BASE UL(0x0EE70000)
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#define TFW_NVCTR_BASE (SOC_TRUSTED_NVCTR_BASE + 0x0000)
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#define TFW_NVCTR_SIZE U(4)
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#define NTFW_CTR_BASE (SOC_TRUSTED_NVCTR_BASE + 0x0004)
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#define NTFW_CTR_SIZE U(4)
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/* Keys */
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#define SOC_KEYS_BASE UL(0x0EE80000)
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#define TZ_PUB_KEY_HASH_BASE (SOC_KEYS_BASE + 0x0000)
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#define TZ_PUB_KEY_HASH_SIZE U(32)
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#define HU_KEY_BASE (SOC_KEYS_BASE + 0x0020)
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#define HU_KEY_SIZE U(16)
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#define END_KEY_BASE (SOC_KEYS_BASE + 0x0044)
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#define END_KEY_SIZE U(32)
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/* Base Element RAM error definitions */
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#define SOC_NS_RAM_ERR_REC_BASE UL(0x2A4C0000)
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#define NS_RAM_ECC_CE_INT U(87)
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#define NS_RAM_ECC_UE_INT U(88)
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#define SOC_PLATFORM_PERIPH_MAP_DEVICE MAP_REGION_FLAT( \
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SOC_PLATFORM_PERIPH_BASE, \
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SOC_PLATFORM_PERIPH_SIZE, \
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MT_DEVICE | MT_RW | MT_SECURE)
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#if SPM_MM
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/*
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* Memory map definition for the platform peripheral memory region that is
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* accessible from S-EL0 (with secure user mode access).
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*/
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#define SOC_PLATFORM_PERIPH_MAP_DEVICE_USER \
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MAP_REGION_FLAT( \
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SOC_PLATFORM_PERIPH_BASE, \
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SOC_PLATFORM_PERIPH_SIZE, \
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MT_DEVICE | MT_RW | MT_SECURE | MT_USER)
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#endif
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#define SOC_SYSTEM_PERIPH_MAP_DEVICE MAP_REGION_FLAT( \
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SOC_SYSTEM_PERIPH_BASE, \
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SOC_SYSTEM_PERIPH_SIZE, \
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MT_DEVICE | MT_RW | MT_SECURE)
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#define SOC_MEMCNTRL_MAP_DEVICE MAP_REGION_FLAT( \
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SOC_MEMCNTRL_BASE, \
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SOC_MEMCNTRL_SIZE, \
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MT_DEVICE | MT_RW | MT_SECURE)
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#define SOC_MEMCNTRL_MAP_DEVICE_REMOTE_CHIP(n) \
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MAP_REGION_FLAT( \
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NRD_REMOTE_CHIP_MEM_OFFSET(n) + SOC_MEMCNTRL_BASE, \
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SOC_MEMCNTRL_SIZE, \
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MT_DEVICE | MT_RW | MT_SECURE)
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/*
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* The bootsec_bridge controls access to a bunch of peripherals, e.g. the UARTs.
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*/
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#define SOC_CSS_NIC400_BOOTSEC_BRIDGE U(5)
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#define SOC_CSS_NIC400_BOOTSEC_BRIDGE_UART1 UL(1 << 12)
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/*
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* Required platform porting definitions common to all ARM CSS SoCs
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*/
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/* 2MB used for SCP DDR retraining */
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#define PLAT_ARM_SCP_TZC_DRAM1_SIZE UL(0x00200000)
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/* V2M motherboard system registers & offsets */
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#define V2M_SYSREGS_BASE UL(0x0C010000)
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#define V2M_SYS_LED U(0x8)
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/*
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* V2M sysled bit definitions. The values written to this
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* register are defined in arch.h & runtime_svc.h. Only
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* used by the primary cpu to diagnose any cold boot issues.
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*
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* SYS_LED[0] - Security state (S=0/NS=1)
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* SYS_LED[2:1] - Exception Level (EL3-EL0)
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* SYS_LED[7:3] - Exception Class (Sync/Async & origin)
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*
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*/
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#define V2M_SYS_LED_SS_SHIFT U(0)
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#define V2M_SYS_LED_EL_SHIFT U(1)
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#define V2M_SYS_LED_EC_SHIFT U(3)
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#define V2M_SYS_LED_SS_MASK U(0x01)
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#define V2M_SYS_LED_EL_MASK U(0x03)
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#define V2M_SYS_LED_EC_MASK U(0x1f)
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/* NOR Flash */
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#define V2M_FLASH0_BASE UL(0x08000000)
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#define V2M_FLASH0_SIZE UL(0x04000000)
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#define V2M_FLASH_BLOCK_SIZE UL(0x00040000) /* 256 KB */
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/*
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* The flash can be mapped either as read-only or read-write.
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*
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* If it is read-write then it should also be mapped as device memory because
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* NOR flash programming involves sending a fixed, ordered sequence of commands.
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*
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* If it is read-only then it should also be mapped as:
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* - Normal memory, because reading from NOR flash is transparent, it is like
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* reading from RAM.
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* - Non-executable by default. If some parts of the flash need to be executable
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* then platform code is responsible for re-mapping the appropriate portion
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* of it as executable.
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*/
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#define V2M_MAP_FLASH0_RW MAP_REGION_FLAT(V2M_FLASH0_BASE,\
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V2M_FLASH0_SIZE, \
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MT_DEVICE | MT_RW | MT_SECURE)
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#define V2M_MAP_FLASH0_RO MAP_REGION_FLAT(V2M_FLASH0_BASE,\
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V2M_FLASH0_SIZE, \
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MT_RO_DATA | MT_SECURE)
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#define NRD_MAP_FLASH0_RO MAP_REGION_FLAT(V2M_FLASH0_BASE,\
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V2M_FLASH0_SIZE, \
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MT_DEVICE | MT_RO | MT_SECURE)
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/* Platform ID address */
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#define BOARD_CSS_PLAT_ID_REG_ADDR UL(0x0EFE00E0)
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/* Platform ID related accessors */
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#define BOARD_CSS_PLAT_ID_REG_ID_MASK U(0x0F)
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#define BOARD_CSS_PLAT_ID_REG_ID_SHIFT U(0x00)
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#define BOARD_CSS_PLAT_ID_REG_VERSION_MASK U(0xF00)
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#define BOARD_CSS_PLAT_ID_REG_VERSION_SHIFT U(0x08)
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#define BOARD_CSS_PLAT_TYPE_RTL U(0x00)
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#define BOARD_CSS_PLAT_TYPE_FPGA U(0x01)
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#define BOARD_CSS_PLAT_TYPE_EMULATOR U(0x02)
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#define BOARD_CSS_PLAT_TYPE_FVP U(0x03)
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#ifndef __ASSEMBLER__
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#include <lib/mmio.h>
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#define BOARD_CSS_GET_PLAT_TYPE(addr) \
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((mmio_read_32(addr) & BOARD_CSS_PLAT_ID_REG_ID_MASK) \
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>> BOARD_CSS_PLAT_ID_REG_ID_SHIFT)
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#endif /* __ASSEMBLER__ */
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#define MAX_IO_DEVICES U(3)
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#define MAX_IO_HANDLES U(4)
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/* Reserve the last block of flash for PSCI MEM PROTECT flag */
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#define PLAT_ARM_FLASH_IMAGE_BASE V2M_FLASH0_BASE
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#define PLAT_ARM_FLASH_IMAGE_MAX_SIZE (V2M_FLASH0_SIZE - V2M_FLASH_BLOCK_SIZE)
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#if ARM_GPT_SUPPORT
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/*
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* Offset of the FIP in the GPT image. BL1 component uses this option
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* as it does not load the partition table to get the FIP base
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* address. At sector 34 by default (i.e. after reserved sectors 0-33)
|
||||
* Offset = 34 * 512(sector size) = 17408 i.e. 0x4400
|
||||
*/
|
||||
#define PLAT_ARM_FIP_OFFSET_IN_GPT 0x4400
|
||||
#endif /* ARM_GPT_SUPPORT */
|
||||
|
||||
#define PLAT_ARM_NVM_BASE V2M_FLASH0_BASE
|
||||
#define PLAT_ARM_NVM_SIZE (V2M_FLASH0_SIZE - V2M_FLASH_BLOCK_SIZE)
|
||||
|
||||
#endif /* NRD_SOC_CSS_DEF_V2_H */
|
||||
Loading…
Add table
Reference in a new issue