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refactor(neoverse-rd): move defines out of platform_def.h

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Presently, the second generation platforms have direct references to CSS
and ROS specific addresses within RD-N2's platform header file
(platform_def.h).  Moreover, there are platform port specific macros
defined within platform_def.h To enhance organization and
appropriateness, relocate these definitions to nrd_css_def2.h,
nrd_ros_def2.h and nrd_arm_platform_def1.h files accordingly.  Reuse
these definitions within the platform_def.h files as needed.

Additionally, remove reference to the unused PLAT_ARM_GICC_BASE macro
from the individual platform_def.h file.

Signed-off-by: Rohit Mathew <rohit.mathew@arm.com>
Change-Id: I9a237c3ae28d7e209188e2c37c8494b4a420ee83
This commit is contained in:
Rohit Mathew 2024-02-26 20:36:13 +00:00
parent 7f693bd993
commit c396c823a3
3 changed files with 74 additions and 69 deletions
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6
plat/arm/board/neoverse_rd/common/include/nrd2/nrd_css_def2.h
View file

@ -38,4 +38,10 @@
/*Secure Watchdog */
#define NRD_CSS_SECURE_WDOG_BASE UL(0x2A480000)
/* MHU */
#define NRD_CSS_AP_SCP_S_MHU_BASE UL(0x2A920000)
/* GIC */
#define NRD_CSS_GIC_BASE UL(0x30000000)
#endif /* NRD_CSS_DEF2_H */

69
plat/arm/board/neoverse_rd/common/include/nrd2/nrd_plat_arm_def2.h
View file

@ -32,6 +32,28 @@
NRD_MAX_CPUS_PER_CLUSTER * \
NRD_MAX_PE_PER_CPU)
#if (NRD_PLATFORM_VARIANT == 1)
#define PLAT_ARM_CLUSTER_COUNT U(8)
#elif (NRD_PLATFORM_VARIANT == 2)
#define PLAT_ARM_CLUSTER_COUNT U(4)
#else
#define PLAT_ARM_CLUSTER_COUNT U(16)
#endif
/*******************************************************************************
* PA/VA config
******************************************************************************/
#ifdef __aarch64__
#define PLAT_PHY_ADDR_SPACE_SIZE NRD_REMOTE_CHIP_MEM_OFFSET( \
NRD_CHIP_COUNT)
#define PLAT_VIRT_ADDR_SPACE_SIZE NRD_REMOTE_CHIP_MEM_OFFSET( \
NRD_CHIP_COUNT)
#else
#define PLAT_PHY_ADDR_SPACE_SIZE (1ULL << 32)
#define PLAT_VIRT_ADDR_SPACE_SIZE (1ULL << 32)
#endif
/*******************************************************************************
* XLAT definitions
******************************************************************************/
@ -201,6 +223,17 @@ ENABLE_FEAT_RAS && FFH_SUPPORT
* GIC/EHF config
******************************************************************************/
/* GIC related constants */
#define PLAT_ARM_GICD_BASE NRD_CSS_GIC_BASE
#if (NRD_PLATFORM_VARIANT == 1)
#define PLAT_ARM_GICR_BASE NRD_CSS_GIC_BASE + UL(0x00100000)
#elif (NRD_PLATFORM_VARIANT == 3)
#define PLAT_ARM_GICR_BASE NRD_CSS_GIC_BASE + UL(0x00300000)
#else
#define PLAT_ARM_GICR_BASE NRD_CSS_GIC_BASE + UL(0x001C0000)
#endif
#define PLAT_ARM_G1S_IRQ_PROPS(grp) CSS_G1S_IRQ_PROPS(grp)
#define PLAT_ARM_G0_IRQ_PROPS(grp) ARM_G0_IRQ_PROPS(grp)
@ -210,6 +243,39 @@ ENABLE_FEAT_RAS && FFH_SUPPORT
#define PLAT_SP_PRI (0x10)
#endif
/* Interrupt priority level for shutdown/reboot */
#define PLAT_REBOOT_PRI GIC_HIGHEST_SEC_PRIORITY
#define PLAT_EHF_DESC EHF_PRI_DESC(PLAT_PRI_BITS, PLAT_REBOOT_PRI)
/*******************************************************************************
* Secure world config
******************************************************************************/
#define SECURE_PARTITION_COUNT 1
#define NS_PARTITION_COUNT 1
#define MAX_EL3_LP_DESCS_COUNT 1
/*******************************************************************************
* MHU config
******************************************************************************/
#define PLAT_CSS_MHU_BASE NRD_CSS_AP_SCP_S_MHU_BASE
#define PLAT_MHUV2_BASE PLAT_CSS_MHU_BASE
/*******************************************************************************
* Power config
******************************************************************************/
#define CSS_SYSTEM_PWR_DMN_LVL ARM_PWR_LVL2
#define PLAT_MAX_PWR_LVL ARM_PWR_LVL1
/*******************************************************************************
* TZ config
******************************************************************************/
#define PLAT_ARM_TZC_BASE NRD_ROS_MEMCNTRL_BASE + UL(0x00720000)
#define PLAT_ARM_TZC_FILTERS TZC_400_REGION_ATTR_FILTER_BIT(0)
/*******************************************************************************
* SDS config
******************************************************************************/
@ -237,8 +303,9 @@ ENABLE_FEAT_RAS && FFH_SUPPORT
#define V2M_SYS_LED_EL_MASK U(0x03)
#define V2M_SYS_LED_EC_MASK U(0x1f)
#define V2M_SYSREGS_BASE UL(0x0C010000)
#define PLAT_ARM_MEM_PROTEC_VA_FRAME UL(0xC0000000)
#define V2M_SYSREGS_BASE UL(0x0C010000)
#define V2M_FLASH0_BASE UL(0x08000000)
#define V2M_FLASH0_SIZE UL(0x04000000)
#define V2M_FLASH_BLOCK_SIZE UL(0x00040000) /* 256 KB */

68
plat/arm/board/neoverse_rd/platform/rdn2/include/platform_def.h
View file

@ -18,14 +18,6 @@
#define NRD_REMOTE_CHIP_MEM_OFFSET(n) \
((ULL(1) << NRD_ADDR_BITS_PER_CHIP) * (n))
#if (NRD_PLATFORM_VARIANT == 1)
#define PLAT_ARM_CLUSTER_COUNT U(8)
#elif (NRD_PLATFORM_VARIANT == 2)
#define PLAT_ARM_CLUSTER_COUNT U(4)
#else
#define PLAT_ARM_CLUSTER_COUNT U(16)
#endif
#define NRD_MAX_CPUS_PER_CLUSTER U(1)
#define NRD_MAX_PE_PER_CPU U(1)
@ -41,16 +33,6 @@
/* DRAM2 */
#define NRD_CSS_DRAM2_SIZE ULL(0x180000000) /* 6GB */
#define PLAT_CSS_MHU_BASE UL(0x2A920000)
#define PLAT_MHUV2_BASE PLAT_CSS_MHU_BASE
#define CSS_SYSTEM_PWR_DMN_LVL ARM_PWR_LVL2
#define PLAT_MAX_PWR_LVL ARM_PWR_LVL1
/* TZC Related Constants */
#define PLAT_ARM_TZC_BASE UL(0x10720000)
#define PLAT_ARM_TZC_FILTERS TZC_400_REGION_ATTR_FILTER_BIT(0)
#define TZC400_OFFSET UL(0x1000000)
#if (NRD_PLATFORM_VARIANT == 1)
@ -86,60 +68,10 @@
/*
* Physical and virtual address space limits for MMU in AARCH64 & AARCH32 modes
*/
#ifdef __aarch64__
#if (NRD_PLATFORM_VARIANT == 2)
#define NRD_ADDR_BITS_PER_CHIP U(46) /* 64TB */
#else
#define NRD_ADDR_BITS_PER_CHIP U(42) /* 4TB */
#endif
#define PLAT_PHY_ADDR_SPACE_SIZE NRD_REMOTE_CHIP_MEM_OFFSET( \
NRD_CHIP_COUNT)
#define PLAT_VIRT_ADDR_SPACE_SIZE NRD_REMOTE_CHIP_MEM_OFFSET( \
NRD_CHIP_COUNT)
#else
#define PLAT_PHY_ADDR_SPACE_SIZE (1ULL << 32)
#define PLAT_VIRT_ADDR_SPACE_SIZE (1ULL << 32)
#endif
/* GIC related constants */
#define PLAT_ARM_GICD_BASE UL(0x30000000)
#define PLAT_ARM_GICC_BASE UL(0x2C000000)
/* Virtual address used by dynamic mem_protect for chunk_base */
#define PLAT_ARM_MEM_PROTEC_VA_FRAME UL(0xC0000000)
#if (NRD_PLATFORM_VARIANT == 1)
#define PLAT_ARM_GICR_BASE UL(0x30100000)
#elif (NRD_PLATFORM_VARIANT == 3)
#define PLAT_ARM_GICR_BASE UL(0x30300000)
#else
#define PLAT_ARM_GICR_BASE UL(0x301C0000)
#endif
/* Interrupt priority level for shutdown/reboot */
#define PLAT_REBOOT_PRI GIC_HIGHEST_SEC_PRIORITY
#define PLAT_EHF_DESC EHF_PRI_DESC(PLAT_PRI_BITS, PLAT_REBOOT_PRI)
/*
* Number of Secure Partitions supported.
* SPMC at EL3, uses this count to configure the maximum number of supported
* secure partitions.
*/
#define SECURE_PARTITION_COUNT 1
/*
* Number of NWd Partitions supported.
* SPMC at EL3, uses this count to configure the maximum number of supported
* nwld partitions.
*/
#define NS_PARTITION_COUNT 1
/*
* Number of Logical Partitions supported.
* SPMC at EL3, uses this count to configure the maximum number of supported
* logical partitions.
*/
#define MAX_EL3_LP_DESCS_COUNT 1
#endif /* PLATFORM_DEF_H */