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refactor(neoverse-rd): set mmap naming convention

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Presently, for the second generation platforms based on the N2 CPU,
macros related to page table entries lack a consistent naming
convention. This absence may lead to potential mix-ups, such as css
definitions in soc files, and can contribute to decreased code clarity.
To address this, establish the following naming convention:

- NRD_CSS_<name>_MMAP for CSS related page table entries
- NRD_ROS_<name>_MMAP for ROS related page table entries

Signed-off-by: Rohit Mathew <rohit.mathew@arm.com>
Change-Id: I7bf1f9b0ddfd0444c802a23143de6a163f127731
This commit is contained in:
Rohit Mathew 2024-03-18 18:20:42 +00:00
parent 4d4763f717
commit edd480d941
4 changed files with 39 additions and 39 deletions
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10
plat/arm/board/neoverse_rd/common/include/nrd2/nrd_css_fw_def2.h
View file

@ -60,20 +60,20 @@
* MMU mapping
******************************************************************************/
#define ARM_MAP_SHARED_RAM_REMOTE_CHIP(n) \
#define NRD_CSS_SHARED_RAM_REMOTE_CHIP_MMAP(n) \
MAP_REGION_FLAT( \
NRD_REMOTE_CHIP_MEM_OFFSET(n) + \
ARM_SHARED_RAM_BASE, \
ARM_SHARED_RAM_SIZE, \
MT_NON_CACHEABLE | MT_RW | MT_SECURE)
#define NRD_MAP_DEVICE \
#define NRD_CSS_PERIPH_MMAP \
MAP_REGION_FLAT( \
NRD_DEVICE_BASE, \
NRD_DEVICE_SIZE, \
MT_DEVICE | MT_RW | MT_SECURE)
#define NRD_MAP_DEVICE_REMOTE_CHIP(n) \
#define NRD_CSS_PERIPH_REMOTE_CHIP_MMAP(n) \
MAP_REGION_FLAT( \
NRD_REMOTE_CHIP_MEM_OFFSET(n) + \
NRD_DEVICE_BASE, \
@ -86,7 +86,7 @@ ENABLE_FEAT_RAS && FFH_SUPPORT
* CPER buffer memory of 128KB is reserved and it is placed adjacent to the
* memory shared between EL3 and S-EL0.
*/
#define NRD_SP_CPER_BUF_MMAP \
#define NRD_CSS_SP_CPER_BUF_MMAP \
MAP_REGION2( \
NRD_SP_CPER_BUF_BASE, \
NRD_SP_CPER_BUF_BASE, \
@ -96,7 +96,7 @@ ENABLE_FEAT_RAS && FFH_SUPPORT
#endif
#if SPM_MM
#define SOC_PLATFORM_SECURE_UART \
#define NRD_CSS_SECURE_UART_USER_MMAP \
MAP_REGION_FLAT( \
SOC_CSS_SEC_UART_BASE, \
SOC_CSS_UART_SIZE, \

16
plat/arm/board/neoverse_rd/common/include/nrd2/nrd_ros_fw_def2.h
View file

@ -17,7 +17,7 @@
* MMU mapping
******************************************************************************/
#define SOC_PLATFORM_PERIPH_MAP_DEVICE \
#define NRD_ROS_PLATFORM_PERIPH_MMAP \
MAP_REGION_FLAT( \
SOC_PLATFORM_PERIPH_BASE, \
SOC_PLATFORM_PERIPH_SIZE, \
@ -25,46 +25,46 @@
#if SPM_MM
#define SOC_PLATFORM_PERIPH_MAP_DEVICE_USER \
#define NRD_ROS_PLATFORM_PERIPH_USER_MMAP \
MAP_REGION_FLAT( \
SOC_PLATFORM_PERIPH_BASE, \
SOC_PLATFORM_PERIPH_SIZE, \
MT_DEVICE | MT_RW | MT_SECURE | MT_USER)
#endif
#define SOC_SYSTEM_PERIPH_MAP_DEVICE \
#define NRD_ROS_SYSTEM_PERIPH_MMAP \
MAP_REGION_FLAT( \
SOC_SYSTEM_PERIPH_BASE, \
SOC_SYSTEM_PERIPH_SIZE, \
MT_DEVICE | MT_RW | MT_SECURE)
#define SOC_MEMCNTRL_MAP_DEVICE \
#define NRD_ROS_MEMCNTRL_MMAP \
MAP_REGION_FLAT( \
SOC_MEMCNTRL_BASE, \
SOC_MEMCNTRL_SIZE, \
MT_DEVICE | MT_RW | MT_SECURE)
#define SOC_MEMCNTRL_MAP_DEVICE_REMOTE_CHIP(n) \
#define NRD_ROS_MEMCNTRL_REMOTE_CHIP_MMAP(n) \
MAP_REGION_FLAT( \
NRD_REMOTE_CHIP_MEM_OFFSET(n) + \
SOC_MEMCNTRL_BASE, \
SOC_MEMCNTRL_SIZE, \
MT_DEVICE | MT_RW | MT_SECURE)
#define PLAT_ARM_SECURE_MAP_SYSTEMREG \
#define NRD_ROS_SECURE_SYSTEMREG_USER_MMAP \
MAP_REGION_FLAT( \
CSS_SYSTEMREG_DEVICE_BASE, \
CSS_SYSTEMREG_DEVICE_SIZE, \
MT_DEVICE | MT_RW | MT_SECURE | MT_USER)
#define PLAT_ARM_SECURE_MAP_NOR2 \
#define NRD_ROS_SECURE_NOR2_USER_MMAP \
MAP_REGION_FLAT( \
CSS_NOR2_FLASH_DEVICE_BASE, \
CSS_NOR2_FLASH_DEVICE_SIZE, \
MT_DEVICE | MT_RW | MT_SECURE | MT_USER)
#define NRD_MAP_FLASH0_RO \
#define NRD_ROS_FLASH0_RO_MMAP \
MAP_REGION_FLAT( \
V2M_FLASH0_BASE, \
V2M_FLASH0_SIZE, \

40
plat/arm/board/neoverse_rd/common/nrd_plat2.c
View file

@ -24,10 +24,10 @@
#if IMAGE_BL1
const mmap_region_t plat_arm_mmap[] = {
ARM_MAP_SHARED_RAM,
NRD_MAP_FLASH0_RO,
NRD_MAP_DEVICE,
SOC_PLATFORM_PERIPH_MAP_DEVICE,
SOC_SYSTEM_PERIPH_MAP_DEVICE,
NRD_ROS_FLASH0_RO_MMAP,
NRD_CSS_PERIPH_MMAP,
NRD_ROS_PLATFORM_PERIPH_MMAP,
NRD_ROS_SYSTEM_PERIPH_MMAP,
{0}
};
#endif
@ -35,23 +35,23 @@ const mmap_region_t plat_arm_mmap[] = {
#if IMAGE_BL2
const mmap_region_t plat_arm_mmap[] = {
ARM_MAP_SHARED_RAM,
NRD_MAP_FLASH0_RO,
NRD_ROS_FLASH0_RO_MMAP,
#ifdef PLAT_ARM_MEM_PROT_ADDR
ARM_V2M_MAP_MEM_PROTECT,
#endif
NRD_MAP_DEVICE,
SOC_MEMCNTRL_MAP_DEVICE,
SOC_PLATFORM_PERIPH_MAP_DEVICE,
SOC_SYSTEM_PERIPH_MAP_DEVICE,
NRD_CSS_PERIPH_MMAP,
NRD_ROS_MEMCNTRL_MMAP,
NRD_ROS_PLATFORM_PERIPH_MMAP,
NRD_ROS_SYSTEM_PERIPH_MMAP,
ARM_MAP_NS_DRAM1,
#if NRD_CHIP_COUNT > 1
SOC_MEMCNTRL_MAP_DEVICE_REMOTE_CHIP(1),
NRD_ROS_MEMCNTRL_REMOTE_CHIP_MMAP(1),
#endif
#if NRD_CHIP_COUNT > 2
SOC_MEMCNTRL_MAP_DEVICE_REMOTE_CHIP(2),
NRD_ROS_MEMCNTRL_REMOTE_CHIP_MMAP(2),
#endif
#if NRD_CHIP_COUNT > 3
SOC_MEMCNTRL_MAP_DEVICE_REMOTE_CHIP(3),
NRD_ROS_MEMCNTRL_REMOTE_CHIP_MMAP(3),
#endif
#if ARM_BL31_IN_DRAM
ARM_MAP_BL31_SEC_DRAM,
@ -72,9 +72,9 @@ const mmap_region_t plat_arm_mmap[] = {
#ifdef PLAT_ARM_MEM_PROT_ADDR
ARM_V2M_MAP_MEM_PROTECT,
#endif
NRD_MAP_DEVICE,
SOC_PLATFORM_PERIPH_MAP_DEVICE,
SOC_SYSTEM_PERIPH_MAP_DEVICE,
NRD_CSS_PERIPH_MMAP,
NRD_ROS_PLATFORM_PERIPH_MMAP,
NRD_ROS_SYSTEM_PERIPH_MMAP,
#if SPM_MM || (SPMC_AT_EL3 && SPMC_AT_EL3_SEL0_SP)
ARM_SPM_BUF_EL3_MMAP,
#endif
@ -83,14 +83,14 @@ const mmap_region_t plat_arm_mmap[] = {
#if SPM_MM && defined(IMAGE_BL31)
const mmap_region_t plat_arm_secure_partition_mmap[] = {
PLAT_ARM_SECURE_MAP_SYSTEMREG,
PLAT_ARM_SECURE_MAP_NOR2,
SOC_PLATFORM_SECURE_UART,
SOC_PLATFORM_PERIPH_MAP_DEVICE_USER,
NRD_ROS_SECURE_SYSTEMREG_USER_MMAP,
NRD_ROS_SECURE_NOR2_USER_MMAP,
NRD_CSS_SECURE_UART_USER_MMAP,
NRD_ROS_PLATFORM_PERIPH_USER_MMAP,
ARM_SP_IMAGE_MMAP,
ARM_SP_IMAGE_NS_BUF_MMAP,
#if ENABLE_FEAT_RAS && FFH_SUPPORT
NRD_SP_CPER_BUF_MMAP,
NRD_CSS_SP_CPER_BUF_MMAP,
#endif
ARM_SP_IMAGE_RW_MMAP,
ARM_SPM_BUF_EL0_MMAP,

12
plat/arm/board/neoverse_rd/platform/rdn2/rdn2_plat.c
View file

@ -17,16 +17,16 @@
#if (NRD_PLATFORM_VARIANT == 2)
static const mmap_region_t rdn2mc_dynamic_mmap[] = {
#if NRD_CHIP_COUNT > 1
ARM_MAP_SHARED_RAM_REMOTE_CHIP(1),
NRD_MAP_DEVICE_REMOTE_CHIP(1),
NRD_CSS_SHARED_RAM_REMOTE_CHIP_MMAP(1),
NRD_CSS_PERIPH_REMOTE_CHIP_MMAP(1),
#endif
#if NRD_CHIP_COUNT > 2
ARM_MAP_SHARED_RAM_REMOTE_CHIP(2),
NRD_MAP_DEVICE_REMOTE_CHIP(2),
NRD_CSS_SHARED_RAM_REMOTE_CHIP_MMAP(2),
NRD_CSS_PERIPH_REMOTE_CHIP_MMAP(2),
#endif
#if NRD_CHIP_COUNT > 3
ARM_MAP_SHARED_RAM_REMOTE_CHIP(3),
NRD_MAP_DEVICE_REMOTE_CHIP(3),
NRD_CSS_SHARED_RAM_REMOTE_CHIP_MMAP(3),
NRD_CSS_PERIPH_REMOTE_CHIP_MMAP(3),
#endif
};
#endif